Commit b8052599 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'gpio-updates-for-v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux 

Pull gpio updates from Bartosz Golaszewski:
 "One new driver, support for new models in existing ones, dt-bindings
  conversions for several modules and improvements all over the place.

  Summary:

   - new driver for the IDT 79RC3243x GPIO controller

   - device tree bindings coversion to YAML for the following drivers:
     gpio-rk3328-grf, gpio-omap, gpio-davinci, gpio-zynq, gpio-stp,
     gpio-pcf857x

   - cleanup of probe functions in many drivers from Alexandru Ardelean,
     mostly dropping unnecessary calls to platform_set_drvdata() and
     removing error messages where none are needed (handled by the
     subsystem already)

   - several improvements to the core gpiolib and the sysfs interface
     code from Andy Shevchenko

   - conversion of the gpio-xilinx driver to using the bitmap API +
     improvements of suspend/resume handling + minor tweaks

   - convert the gpio-stmpe to using devres helpers exclusively in probe
     for improved robustness

   - updates for the generic gpio-regmap driver

   - updates for the gpio-dwapb driver

   - support for a new model in gpio-pca953x

   - cleanups in gpio-tegra186, gpio-104-idio-16, gpio-mxs & gpio-xgene

   - slight code refactoring of the gpio-zynq driver

   - documentation fixes from Mauro Carvalho Chehab

   - a bunch of minor tweaks and improvements all over the place"

* tag 'gpio-updates-for-v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (57 commits)
  docs: driver-api: gpio: using-gpio.rst: avoid using ReST :doc:`foo` markup
  dt-bindings: gpio: pcf857x: Convert to json-schema
  gpio: mxs: Prefer unsigned int to bare use of unsigned
  dt-bindings: gpio: stp: convert to json-schema
  dt-bindings: gpio: zynq: convert bindings to YAML
  dt-bindings: gpio: gpio-davinci: Convert to json-schema
  gpio: pca953x: Add support for the On Semi pca9655
  gpio: gpio-xilinx: update on suspend and resume calls
  gpio: zynq: Check return value of irq_get_irq_data
  gpio: zynq: Check return value of pm_runtime_get_sync
  gpio: zynq: use module_platform_driver to simplify the code
  gpio: idt3243x: Fix return value check in idt_gpio_probe()
  MAINTAINERS: update ti,omap-gpio.yaml reference
  dt-bindings: gpio: Add devicetree binding for IDT 79RC32434 GPIO controller
  gpio: Add support for IDT 79RC3243x GPIO controller
  gpio: regmap: move drvdata to config data
  gpio-dwapb: Drop unused headers and sort the rest
  gpio: gpio-regmap: Use devm_add_action_or_reset()
  gpio: dwapb: Switch to use fwnode_irq_get()
  gpio: dwapb: Drop redundant check in dwapb_irq_set_type()
  ...
parents 1f89a590 c34c1228

Documentation/devicetree/bindings/gpio/gpio-davinci.txt

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Davinci/Keystone GPIO controller bindings



Required Properties:

- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs

			"ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,

						66AK2E SoCs

			"ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G

			"ti,am654-gpio", "ti,keystone-gpio": for TI K3 AM654

			"ti,j721e-gpio", "ti,keystone-gpio": for J721E SoCs

			"ti,am64-gpio", "ti,keystone-gpio": for AM64 SoCs



- reg: Physical base address of the controller and the size of memory mapped

       registers.



- gpio-controller : Marks the device node as a gpio controller.



- #gpio-cells : Should be two.

  - first cell is the pin number

  - second cell is used to specify optional parameters (unused)



- interrupts: Array of GPIO interrupt number. Only banked or unbanked IRQs are

	      supported at a time.



- ti,ngpio: The number of GPIO pins supported.



- ti,davinci-gpio-unbanked: The number of GPIOs that have an individual interrupt

		            line to processor.



- clocks: Should contain the device's input clock, and should be defined as per

          the appropriate clock bindings consumer usage in,



          Documentation/devicetree/bindings/clock/keystone-gate.txt

                            for 66AK2HK/66AK2L/66AK2E SoCs or,



          Documentation/devicetree/bindings/clock/ti,sci-clk.yaml

                            for 66AK2G SoCs



- clock-names: Name should be "gpio";



Currently clock-names and clocks are needed for all keystone 2 platforms

Davinci platforms do not have DT clocks as of now.



The GPIO controller also acts as an interrupt controller. It uses the default

two cells specifier as described in Documentation/devicetree/bindings/

interrupt-controller/interrupts.txt.



Example:



gpio: gpio@1e26000 {

	compatible = "ti,dm6441-gpio";

	gpio-controller;

	#gpio-cells = <2>;

	reg = <0x226000 0x1000>;

	interrupt-parent = <&intc>;

	interrupts = <42 IRQ_TYPE_EDGE_BOTH 43 IRQ_TYPE_EDGE_BOTH

		44 IRQ_TYPE_EDGE_BOTH 45 IRQ_TYPE_EDGE_BOTH

		46 IRQ_TYPE_EDGE_BOTH 47 IRQ_TYPE_EDGE_BOTH

		48 IRQ_TYPE_EDGE_BOTH 49 IRQ_TYPE_EDGE_BOTH

		50 IRQ_TYPE_EDGE_BOTH>;

	ti,ngpio = <144>;

	ti,davinci-gpio-unbanked = <0>;

	interrupt-controller;

	#interrupt-cells = <2>;

};



leds {

	compatible = "gpio-leds";



	led1 {

		label = "davinci:green:usr1";

		gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;

		...

	};



	led2 {

		label = "davinci:red:debug1";

		gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;

		...

	};

};



Example for 66AK2G:



gpio0: gpio@2603000 {

	compatible = "ti,k2g-gpio", "ti,keystone-gpio";

	reg = <0x02603000 0x100>;

	gpio-controller;

	#gpio-cells = <2>;

	interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;

	interrupt-controller;

	#interrupt-cells = <2>;

	ti,ngpio = <144>;

	ti,davinci-gpio-unbanked = <0>;

	clocks = <&k2g_clks 0x001b 0x0>;

	clock-names = "gpio";

};



Example for 66AK2HK/66AK2L/66AK2E:



gpio0: gpio@260bf00 {

	compatible = "ti,keystone-gpio";

	reg = <0x0260bf00 0x100>;

	gpio-controller;

	#gpio-cells = <2>;

	/* HW Interrupts mapped to GPIO pins */

	interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;

			clocks = <&clkgpio>;

	clock-names = "gpio";

	ti,ngpio = <32>;

	ti,davinci-gpio-unbanked = <32>;

};



Example for K3 AM654:



wkup_gpio0: wkup_gpio0@42110000 {

	compatible = "ti,am654-gpio", "ti,keystone-gpio";

	reg = <0x42110000 0x100>;

	gpio-controller;

	#gpio-cells = <2>;

	interrupt-parent = <&intr_wkup_gpio>;

	interrupts = <59 128>, <59 129>, <59 130>, <59 131>;

	interrupt-controller;

	#interrupt-cells = <2>;

	ti,ngpio = <56>;

	ti,davinci-gpio-unbanked = <0>;

	clocks = <&k3_clks 59 0>;

	clock-names = "gpio";

};

Documentation/devicetree/bindings/gpio/gpio-davinci.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: GPIO controller for Davinci and keystone devices



maintainers:

  - Keerthy <j-keerthy@ti.com>



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - ti,k2g-gpio

              - ti,am654-gpio

              - ti,j721e-gpio

              - ti,am64-gpio

          - const: ti,keystone-gpio



      - items:

          - enum:

              - ti,dm6441-gpio

              - ti,keystone-gpio



  reg:

    maxItems: 1



  gpio-controller: true



  gpio-ranges: true



  gpio-line-names:

    description: strings describing the names of each gpio line.

    minItems: 1

    maxItems: 100



  "#gpio-cells":

    const: 2

    description:

      first cell is the pin number and second cell is used to specify optional parameters (unused).



  interrupts:

    description:

      The interrupts are specified as per the interrupt parent. Only banked

      or unbanked IRQs are supported at a time. If the interrupts are

      banked then provide list of interrupts corresponding to each bank, else

      provide the list of interrupts for each gpio.

    minItems: 1

    maxItems: 100



  ti,ngpio:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: The number of GPIO pins supported consecutively.

    minimum: 1



  ti,davinci-gpio-unbanked:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: The number of GPIOs that have an individual interrupt line to processor.

    minimum: 0



  clocks:

    maxItems: 1



  clock-names:

    const: gpio



  interrupt-controller: true



  power-domains:

    maxItems: 1



  "#interrupt-cells":

    const: 2



patternProperties:

  "^(.+-hog(-[0-9]+)?)$":

    type: object



    required:

      - gpio-hog



required:

  - compatible

  - reg

  - gpio-controller

  - "#gpio-cells"

  - interrupts

  - ti,ngpio

  - ti,davinci-gpio-unbanked

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include<dt-bindings/interrupt-controller/arm-gic.h>



    gpio0: gpio@2603000 {

      compatible = "ti,k2g-gpio", "ti,keystone-gpio";

      reg = <0x02603000 0x100>;

      gpio-controller;

      #gpio-cells = <2>;

      interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;

      interrupt-controller;

      #interrupt-cells = <2>;

      ti,ngpio = <144>;

      ti,davinci-gpio-unbanked = <0>;

      clocks = <&k2g_clks 0x001b 0x0>;

      clock-names = "gpio";

    };



  - |

    #include<dt-bindings/interrupt-controller/arm-gic.h>



    gpio1: gpio@260bf00 {

      compatible = "ti,keystone-gpio";

      reg = <0x0260bf00 0x100>;

      gpio-controller;

      #gpio-cells = <2>;

      /* HW Interrupts mapped to GPIO pins */

      interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;

      clocks = <&clkgpio>;

      clock-names = "gpio";

      ti,ngpio = <32>;

      ti,davinci-gpio-unbanked = <32>;

    };



  - |

    wkup_gpio0: gpio0@42110000 {

      compatible = "ti,am654-gpio", "ti,keystone-gpio";

      reg = <0x42110000 0x100>;

      gpio-controller;

      #gpio-cells = <2>;

      interrupt-parent = <&intr_wkup_gpio>;

      interrupts = <60>, <61>, <62>, <63>;

      interrupt-controller;

      #interrupt-cells = <2>;

      ti,ngpio = <56>;

      ti,davinci-gpio-unbanked = <0>;

      clocks = <&k3_clks 59 0>;

      clock-names = "gpio";

    };

Documentation/devicetree/bindings/gpio/gpio-omap.txt

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OMAP GPIO controller bindings



Required properties:

- compatible:

  - "ti,omap2-gpio" for OMAP2 controllers

  - "ti,omap3-gpio" for OMAP3 controllers

  - "ti,omap4-gpio" for OMAP4 controllers

- reg : Physical base address of the controller and length of memory mapped

  region.

- gpio-controller : Marks the device node as a GPIO controller.

- #gpio-cells : Should be two.

  - first cell is the pin number

  - second cell is used to specify optional parameters (unused)

- interrupt-controller: Mark the device node as an interrupt controller.

- #interrupt-cells : Should be 2.

  The first cell is the GPIO number.

  The second cell is used to specify flags:

    bits[3:0] trigger type and level flags:

      1 = low-to-high edge triggered.

      2 = high-to-low edge triggered.

      4 = active high level-sensitive.

      8 = active low level-sensitive.

- interrupts : The interrupt the controller is rising as output when an

  interrupt occures



OMAP specific properties:

- ti,hwmods:		Name of the hwmod associated to the GPIO:

			"gpio<X>", <X> being the 1-based instance number

			from the HW spec.

- ti,gpio-always-on: 	Indicates if a GPIO bank is always powered and

			so will never lose its logic state.





Example:



gpio0: gpio@44e07000 {

    compatible = "ti,omap4-gpio";

    reg = <0x44e07000 0x1000>;

    ti,hwmods = "gpio1";

    gpio-controller;

    #gpio-cells = <2>;

    interrupt-controller;

    #interrupt-cells = <2>;

    interrupts = <96>;

};

Documentation/devicetree/bindings/gpio/gpio-pcf857x.txt

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* PCF857x-compatible I/O expanders



The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be

driven high by a pull-up current source or driven low to ground. This combines

the direction and output level into a single bit per line, which can't be read

back. We can't actually know at initialization time whether a line is configured

(a) as output and driving the signal low/high, or (b) as input and reporting a

low/high value, without knowing the last value written since the chip came out

of reset (if any). The only reliable solution for setting up line direction is

thus to do it explicitly.



Required Properties:



  - compatible: should be one of the following.

    - "maxim,max7328": For the Maxim MAX7378

    - "maxim,max7329": For the Maxim MAX7329

    - "nxp,pca8574": For the NXP PCA8574

    - "nxp,pca8575": For the NXP PCA8575

    - "nxp,pca9670": For the NXP PCA9670

    - "nxp,pca9671": For the NXP PCA9671

    - "nxp,pca9672": For the NXP PCA9672

    - "nxp,pca9673": For the NXP PCA9673

    - "nxp,pca9674": For the NXP PCA9674

    - "nxp,pca9675": For the NXP PCA9675

    - "nxp,pcf8574": For the NXP PCF8574

    - "nxp,pcf8574a": For the NXP PCF8574A

    - "nxp,pcf8575": For the NXP PCF8575



  - reg: I2C slave address.



  - gpio-controller: Marks the device node as a gpio controller.

  - #gpio-cells: Should be 2. The first cell is the GPIO number and the second

    cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the

    GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.



Optional Properties:



  - lines-initial-states: Bitmask that specifies the initial state of each

  line. When a bit is set to zero, the corresponding line will be initialized to

  the input (pulled-up) state. When the  bit is set to one, the line will be

  initialized the low-level output state. If the property is not specified

  all lines will be initialized to the input state.



  The I/O expander can detect input state changes, and thus optionally act as

  an interrupt controller. When the expander interrupt line is connected all the

  following properties must be set. For more information please see the

  interrupt controller device tree bindings documentation available at

  Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.



  - interrupt-controller: Identifies the node as an interrupt controller.

  - #interrupt-cells: Number of cells to encode an interrupt source, shall be 2.

  - interrupts: Interrupt specifier for the controllers interrupt.





Please refer to gpio.txt in this directory for details of the common GPIO

bindings used by client devices.



Example: PCF8575 I/O expander node



	pcf8575: gpio@20 {

		compatible = "nxp,pcf8575";

		reg = <0x20>;

		interrupt-parent = <&irqpin2>;

		interrupts = <3 0>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};

Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt

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Lantiq SoC Serial To Parallel (STP) GPIO controller



The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a

peripheral controller used to drive external shift register cascades. At most

3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem

to drive the 2 LSBs of the cascade automatically.





Required properties:

- compatible : Should be "lantiq,gpio-stp-xway"

- reg : Address and length of the register set for the device

- #gpio-cells : Should be two.  The first cell is the pin number and

  the second cell is used to specify optional parameters (currently

  unused).

- gpio-controller : Marks the device node as a gpio controller.



Optional properties:

- lantiq,shadow : The default value that we shall assume as already set on the

  shift register cascade.

- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled

  in the shift register cascade.

- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit

  property can enable this feature.

- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade.

- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade.

- lantiq,rising : use rising instead of falling edge for the shift register



Example:



gpio1: stp@e100bb0 {

	compatible = "lantiq,gpio-stp-xway";

	reg = <0xE100BB0 0x40>;

	#gpio-cells = <2>;

	gpio-controller;



	lantiq,shadow = <0xffff>;

	lantiq,groups = <0x7>;

	lantiq,dsl = <0x3>;

	lantiq,phy1 = <0x7>;

	lantiq,phy2 = <0x7>;

	/* lantiq,rising; */

};