Commit b7feaa49 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-fix-v6.4-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi fixes from Mark Brown:
 "A few more driver specific fixes.

  The DesignWare fix is for an issue introduced by conversion to the
  chip select accessor functions and is pretty important but the other
  two are less severe"

* tag 'spi-fix-v6.4-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
  spi: dw: Replace incorrect spi_get_chipselect with set
  spi: fsl-dspi: avoid SCK glitches with continuous transfers
  spi: cadence-quadspi: Add missing check for dma_set_mask
parents eee71c34 eee43699

drivers/spi/spi-cadence-quadspi.c

+5 −2
Original line number Diff line number Diff line
@@ -1756,8 +1756,11 @@ static int cqspi_probe(struct platform_device *pdev) 
			cqspi->slow_sram = true;



		if (of_device_is_compatible(pdev->dev.of_node,

					    "xlnx,versal-ospi-1.0"))

			dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));

					    "xlnx,versal-ospi-1.0")) {

			ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));

			if (ret)

				goto probe_reset_failed;

		}

	}



	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,

drivers/spi/spi-dw-mmio.c

+1 −1
Original line number Diff line number Diff line
@@ -274,7 +274,7 @@ static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) 
	 */

	spi_set_chipselect(spi, 0, 0);

	dw_spi_set_cs(spi, enable);

	spi_get_chipselect(spi, cs);

	spi_set_chipselect(spi, 0, cs);

}



static int dw_spi_elba_init(struct platform_device *pdev,

drivers/spi/spi-fsl-dspi.c

+15 −0
Original line number Diff line number Diff line
@@ -1002,7 +1002,9 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, 
static int dspi_setup(struct spi_device *spi)

{

	struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);

	u32 period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->max_speed_hz);

	unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;

	u32 quarter_period_ns = DIV_ROUND_UP(period_ns, 4);

	u32 cs_sck_delay = 0, sck_cs_delay = 0;

	struct fsl_dspi_platform_data *pdata;

	unsigned char pasc = 0, asc = 0;
@@ -1031,6 +1033,19 @@ static int dspi_setup(struct spi_device *spi) 
		sck_cs_delay = pdata->sck_cs_delay;

	}



	/* Since tCSC and tASC apply to continuous transfers too, avoid SCK

	 * glitches of half a cycle by never allowing tCSC + tASC to go below

	 * half a SCK period.

	 */

	if (cs_sck_delay < quarter_period_ns)

		cs_sck_delay = quarter_period_ns;

	if (sck_cs_delay < quarter_period_ns)

		sck_cs_delay = quarter_period_ns;



	dev_dbg(&spi->dev,

		"DSPI controller timing params: CS-to-SCK delay %u ns, SCK-to-CS delay %u ns\n",

		cs_sck_delay, sck_cs_delay);



	clkrate = clk_get_rate(dspi->clk);

	hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);