Commit b7fbef00 authored by Sandipan Das's avatar Sandipan Das Committed by PrithivishS
Browse files

perf vendor events amd: Add Zen 5 uncore events 

mainline inclusion
from mainline-v6.10-rc1
commit dc082ae61858dc262fd3a482846fb0fe4b947f33
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IAYOV8
CVE: NA

Reference: https://github.com/torvalds/linux/commit/dc082ae61858dc262fd3a482846fb0fe4b947f33



--------------------------------

commit dc082ae61858dc262fd3a482846fb0fe4b947f33 upstream

Add uncore events taken from Section 1.5 "L3 Cache Performance Monitor
Counters" and Section 2 "UMC Performance Monitors" of the Performance
Monitor Counters for AMD Family 1Ah Model 00h-0Fh Processors document
available at the link below.

This constitutes events which capture L3 cache and UMC command activity.

Reviewed-by: default avatarIan Rogers <irogers@google.com>
Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Link: https://bugzilla.kernel.org/attachment.cgi?id=305974
Link: https://lore.kernel.org/r/e11e8d9d1af34a0fb565fc9d1c4a05f569c39ddc.1714717230.git.sandipan.das@amd.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: default avatarsuryasaimadhu <SaiMadhu.KoyyalaHariVenkata@amd.com>
Signed-off-by: default avatarPrithivishS <sprithiv@amd.com>
parent 403779a8

tools/perf/pmu-events/arch/x86/amdzen5/l3-cache.json

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[

  {

    "EventName": "l3_lookup_state.l3_miss",

    "EventCode": "0x04",

    "BriefDescription": "L3 cache misses.",

    "UMask": "0x01",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_lookup_state.l3_hit",

    "EventCode": "0x04",

    "BriefDescription": "L3 cache hits.",

    "UMask": "0xfe",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_lookup_state.all_coherent_accesses_to_l3",

    "EventCode": "0x04",

    "BriefDescription": "L3 cache requests for all coherent accesses.",

    "UMask": "0xff",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency.dram_near",

    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.",

    "UMask": "0x01",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency.dram_far",

    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA node.",

    "UMask": "0x02",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency.near_cache",

    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node.",

    "UMask": "0x04",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency.far_cache",

    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node.",

    "UMask": "0x08",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency.ext_near",

    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node.",

    "UMask": "0x10",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency.ext_far",

    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node.",

    "UMask": "0x20",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency.all",

    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency from all data sources.",

    "UMask": "0x3f",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency_requests.dram_near",

    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",

    "UMask": "0x01",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency_requests.dram_far",

    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",

    "UMask": "0x02",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency_requests.near_cache",

    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node.",

    "UMask": "0x04",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency_requests.far_cache",

    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node.",

    "UMask": "0x08",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency_requests.ext_near",

    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node.",

    "UMask": "0x10",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency_requests.ext_far",

    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node.",

    "UMask": "0x20",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_xi_sampled_latency_requests.all",

    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from all data sources.",

    "UMask": "0x3f",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  }

]

tools/perf/pmu-events/arch/x86/amdzen5/memory-controller.json

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[

  {

    "EventName": "umc_mem_clk",

    "PublicDescription": "Number of memory clock (MEMCLK) cycles.",

    "EventCode": "0x00",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_act_cmd.all",

    "PublicDescription": "Number of ACTIVATE commands sent.",

    "EventCode": "0x05",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_act_cmd.rd",

    "PublicDescription": "Number of ACTIVATE commands sent for reads.",

    "EventCode": "0x05",

    "RdWrMask": "0x1",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_act_cmd.wr",

    "PublicDescription": "Number of ACTIVATE commands sent for writes.",

    "EventCode": "0x05",

    "RdWrMask": "0x2",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_pchg_cmd.all",

    "PublicDescription": "Number of PRECHARGE commands sent.",

    "EventCode": "0x06",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_pchg_cmd.rd",

    "PublicDescription": "Number of PRECHARGE commands sent for reads.",

    "EventCode": "0x06",

    "RdWrMask": "0x1",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_pchg_cmd.wr",

    "PublicDescription": "Number of PRECHARGE commands sent for writes.",

    "EventCode": "0x06",

    "RdWrMask": "0x2",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_cas_cmd.all",

    "PublicDescription": "Number of CAS commands sent.",

    "EventCode": "0x0a",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_cas_cmd.rd",

    "PublicDescription": "Number of CAS commands sent for reads.",

    "EventCode": "0x0a",

    "RdWrMask": "0x1",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_cas_cmd.wr",

    "PublicDescription": "Number of CAS commands sent for writes.",

    "EventCode": "0x0a",

    "RdWrMask": "0x2",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_data_slot_clks.all",

    "PublicDescription": "Number of clock cycles used by the data bus.",

    "EventCode": "0x14",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_data_slot_clks.rd",

    "PublicDescription": "Number of clock cycles used by the data bus for reads.",

    "EventCode": "0x14",

    "RdWrMask": "0x1",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_data_slot_clks.wr",

    "PublicDescription": "Number of clock cycles used by the data bus for writes.",

    "EventCode": "0x14",

    "RdWrMask": "0x2",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  }

]