Commit b7fb767b authored by jason-jh.lin's avatar jason-jh.lin Committed by Chun-Kuang Hu
Browse files

drm/mediatek: Add DSC support for mediatek-drm 

DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220526102126.19756-2-jason-jh.lin@mediatek.com/


Signed-off-by: default avatarjason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarChun-Kuang Hu <chunkuang.hu@kernel.org>
parent f2906aa8

drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c

+47 −0
Original line number Diff line number Diff line
@@ -40,6 +40,12 @@ 
#define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)

#define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)



#define DISP_REG_DSC_CON			0x0000

#define DSC_EN					BIT(0)

#define DSC_DUAL_INOUT				BIT(2)

#define DSC_BYPASS				BIT(4)

#define DSC_UFOE_SEL				BIT(16)



#define DISP_REG_OD_EN				0x0000

#define DISP_REG_OD_CFG				0x0020

#define OD_RELAYMODE				BIT(0)
@@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc, 
			      DISP_DITHERING, cmdq_pkt);

}



static void mtk_dsc_config(struct device *dev, unsigned int w,

			   unsigned int h, unsigned int vrefresh,

			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	/* dsc bypass mode */

	mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,

			   DISP_REG_DSC_CON, DSC_BYPASS);

	mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,

			   DISP_REG_DSC_CON, DSC_UFOE_SEL);

	mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,

			   DISP_REG_DSC_CON, DSC_DUAL_INOUT);

}



static void mtk_dsc_start(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	/* write with mask to reserve the value set in mtk_dsc_config */

	mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);

}



static void mtk_dsc_stop(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);

}



static void mtk_od_config(struct device *dev, unsigned int w,

			  unsigned int h, unsigned int vrefresh,

			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = { 
	.stop = mtk_dpi_stop,

};



static const struct mtk_ddp_comp_funcs ddp_dsc = {

	.clk_enable = mtk_ddp_clk_enable,

	.clk_disable = mtk_ddp_clk_disable,

	.config = mtk_dsc_config,

	.start = mtk_dsc_start,

	.stop = mtk_dsc_stop,

};



static const struct mtk_ddp_comp_funcs ddp_dsi = {

	.start = mtk_dsi_ddp_start,

	.stop = mtk_dsi_ddp_stop,
@@ -343,6 +387,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { 
	[MTK_DISP_CCORR] = "ccorr",

	[MTK_DISP_COLOR] = "color",

	[MTK_DISP_DITHER] = "dither",

	[MTK_DISP_DSC] = "dsc",

	[MTK_DISP_GAMMA] = "gamma",

	[MTK_DISP_MUTEX] = "mutex",

	[MTK_DISP_OD] = "od",
@@ -373,6 +418,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { 
	[DDP_COMPONENT_DITHER]		= { MTK_DISP_DITHER,	0, &ddp_dither },

	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },

	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },

	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,	0, &ddp_dsc },

	[DDP_COMPONENT_DSC1]		= { MTK_DISP_DSC,	1, &ddp_dsc },

	[DDP_COMPONENT_DSI0]		= { MTK_DSI,		0, &ddp_dsi },

	[DDP_COMPONENT_DSI1]		= { MTK_DSI,		1, &ddp_dsi },

	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },

drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type { 
	MTK_DISP_CCORR,

	MTK_DISP_COLOR,

	MTK_DISP_DITHER,

	MTK_DISP_DSC,

	MTK_DISP_GAMMA,

	MTK_DISP_MUTEX,

	MTK_DISP_OD,