Commit b7e2fba0 authored by Bryan O'Donoghue's avatar Bryan O'Donoghue Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8250: Add UFS controller and PHY 



Add nodes for the UFS controller and PHY, and enable these for the MTP
with relevant supplies specified.

Tested-by: default avatarVinod Koul <vkoul@kernel.org>
Reviewed-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20200415061430.740854-3-bjorn.andersson@linaro.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent ec13d5c2

arch/arm64/boot/dts/qcom/sm8250-mtp.dts

+20 −0
Original line number Diff line number Diff line
@@ -358,3 +358,23 @@ 
&uart2 {

	status = "okay";

};



&ufs_mem_hc {

	status = "okay";



	vcc-supply = <&vreg_l17a_3p0>;

	vcc-max-microamp = <750000>;

	vccq-supply = <&vreg_l6a_1p2>;

	vccq-max-microamp = <700000>;

	vccq2-supply = <&vreg_s4a_1p8>;

	vccq2-max-microamp = <750000>;

};



&ufs_mem_phy {

	status = "okay";



	vdda-phy-supply = <&vreg_l5a_0p875>;

	vdda-max-microamp = <90200>;

	vdda-pll-supply = <&vreg_l9a_1p2>;

	vdda-pll-max-microamp = <19000>;

};

arch/arm64/boot/dts/qcom/sm8250.dtsi

+71 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-sm8250.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/power/qcom-rpmpd.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -305,6 +306,76 @@ 
			};

		};



		ufs_mem_hc: ufs@1d84000 {

			compatible = "qcom,sm8250-ufshc", "qcom,ufshc",

				     "jedec,ufs-2.0";

			reg = <0 0x01d84000 0 0x3000>;

			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

			phys = <&ufs_mem_phy_lanes>;

			phy-names = "ufsphy";

			lanes-per-direction = <2>;

			#reset-cells = <1>;

			resets = <&gcc GCC_UFS_PHY_BCR>;

			reset-names = "rst";



			power-domains = <&gcc UFS_PHY_GDSC>;



			clock-names =

				"core_clk",

				"bus_aggr_clk",

				"iface_clk",

				"core_clk_unipro",

				"ref_clk",

				"tx_lane0_sync_clk",

				"rx_lane0_sync_clk",

				"rx_lane1_sync_clk";

			clocks =

				<&gcc GCC_UFS_PHY_AXI_CLK>,

				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

				<&gcc GCC_UFS_PHY_AHB_CLK>,

				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

				<&rpmhcc RPMH_CXO_CLK>,

				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

			freq-table-hz =

				<37500000 300000000>,

				<0 0>,

				<0 0>,

				<37500000 300000000>,

				<0 0>,

				<0 0>,

				<0 0>,

				<0 0>;



			status = "disabled";

		};



		ufs_mem_phy: phy@1d87000 {

			compatible = "qcom,sm8250-qmp-ufs-phy";

			reg = <0 0x01d87000 0 0x1c0>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			clock-names = "ref",

				      "ref_aux";

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;



			resets = <&ufs_mem_hc 0>;

			reset-names = "ufsphy";

			status = "disabled";



			ufs_mem_phy_lanes: lanes@1d87400 {

				reg = <0 0x01d87400 0 0x108>,

				      <0 0x01d87600 0 0x1e0>,

				      <0 0x01d87c00 0 0x1dc>,

				      <0 0x01d87800 0 0x108>,

				      <0 0x01d87a00 0 0x1e0>;

				#phy-cells = <0>;

			};

		};



		intc: interrupt-controller@17a00000 {

			compatible = "arm,gic-v3";

			#interrupt-cells = <3>;