Commit b7d15590 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: move dbuf under display sub-struct 



Move display dbuf related members under drm_i915_private display
sub-struct.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3363a516c12bd8bfb240131e9eb9fc3a0f3057a3.1661779055.git.jani.nikula@intel.com
parent 5da6d6c7

drivers/gpu/drm/i915/display/intel_display_core.h

+7 −0
Original line number Diff line number Diff line
@@ -299,6 +299,13 @@ struct intel_display { 
		unsigned int max_cdclk_freq;

	} cdclk;



	struct {

		/* The current hardware dbuf configuration */

		u8 enabled_slices;



		struct intel_global_obj obj;

	} dbuf;



	struct {

		/* VLV/CHV/BXT/GLK DSI MMIO register base address */

		u32 mmio_base;

drivers/gpu/drm/i915/display/intel_display_power.c

+3 −3
Original line number Diff line number Diff line
@@ -1061,14 +1061,14 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 
	for_each_dbuf_slice(dev_priv, slice)

		gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));



	dev_priv->dbuf.enabled_slices = req_slices;

	dev_priv->display.dbuf.enabled_slices = req_slices;



	mutex_unlock(&power_domains->lock);

}



static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)

{

	dev_priv->dbuf.enabled_slices =

	dev_priv->display.dbuf.enabled_slices =

		intel_enabled_dbuf_slices_mask(dev_priv);



	/*
@@ -1076,7 +1076,7 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) 
	 * figure out later which slices we have and what we need.

	 */

	gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |

				dev_priv->dbuf.enabled_slices);

				dev_priv->display.dbuf.enabled_slices);

}



static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/display/intel_display_power_well.c

+1 −1
Original line number Diff line number Diff line
@@ -946,7 +946,7 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 
static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)

{

	u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);

	u8 enabled_dbuf_slices = dev_priv->dbuf.enabled_slices;

	u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices;



	drm_WARN(&dev_priv->drm,

		 hw_enabled_dbuf_slices != enabled_dbuf_slices,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

+2 −2
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 
	struct intel_cdclk_state *cdclk_state =

		to_intel_cdclk_state(i915->display.cdclk.obj.state);

	struct intel_dbuf_state *dbuf_state =

		to_intel_dbuf_state(i915->dbuf.obj.state);

		to_intel_dbuf_state(i915->display.dbuf.obj.state);

	struct intel_crtc_state *crtc_state =

		to_intel_crtc_state(crtc->base.state);

	struct intel_plane *plane;
@@ -417,7 +417,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) 
	struct intel_cdclk_state *cdclk_state =

		to_intel_cdclk_state(i915->display.cdclk.obj.state);

	struct intel_dbuf_state *dbuf_state =

		to_intel_dbuf_state(i915->dbuf.obj.state);

		to_intel_dbuf_state(i915->display.dbuf.obj.state);

	enum pipe pipe;

	struct intel_crtc *crtc;

	struct intel_encoder *encoder;

drivers/gpu/drm/i915/i915_drv.h

+0 −7
Original line number Diff line number Diff line
@@ -281,13 +281,6 @@ struct drm_i915_private { 
	unsigned int hpll_freq;

	unsigned int czclk_freq;



	struct {

		/* The current hardware dbuf configuration */

		u8 enabled_slices;



		struct intel_global_obj obj;

	} dbuf;



	/**

	 * wq - Driver workqueue for GEM.

	 *