Commit b7cf8a54 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark
Browse files

drm/msm/dsi: move ioremaps to dsi_phy_driver_probe 



All PHY drivers would map dsi_pll area. Some PHY drivers would also
map dsi_phy area again (a leftover from old PHY/PLL separation). Move
all ioremaps to the common dsi_phy driver code and drop individual
ioremapped areas from PHY drivers.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Link: https://lore.kernel.org/r/20210331105735.3690009-21-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent e55b3fbb

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+7 −0
Original line number Diff line number Diff line
@@ -682,6 +682,13 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) 
		goto fail;

	}



	phy->pll_base = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");

	if (IS_ERR(phy->pll_base)) {

		DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);

		ret = -ENOMEM;

		goto fail;

	}



	if (phy->cfg->has_phy_lane) {

		phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE");

		if (IS_ERR(phy->lane_base)) {

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+1 −0
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ struct msm_dsi_dphy_timing { 
struct msm_dsi_phy {

	struct platform_device *pdev;

	void __iomem *base;

	void __iomem *pll_base;

	void __iomem *reg_base;

	void __iomem *lane_base;

	int id;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

+30 −45
Original line number Diff line number Diff line
@@ -91,9 +91,6 @@ struct dsi_pll_10nm { 


	struct msm_dsi_phy *phy;



	void __iomem *phy_cmn_mmio;

	void __iomem *mmio;



	u64 vco_ref_clk_rate;

	u64 vco_current_rate;
@@ -228,7 +225,7 @@ static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll) 


static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll)

{

	void __iomem *base = pll->mmio;

	void __iomem *base = pll->phy->pll_base;

	struct dsi_pll_regs *regs = &pll->reg_setup;



	if (pll->pll_configuration.enable_ssc) {
@@ -253,7 +250,7 @@ static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll) 


static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll)

{

	void __iomem *base = pll->mmio;

	void __iomem *base = pll->phy->pll_base;



	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
@@ -279,7 +276,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll) 


static void dsi_pll_commit(struct dsi_pll_10nm *pll)

{

	void __iomem *base = pll->mmio;

	void __iomem *base = pll->phy->pll_base;

	struct dsi_pll_regs *reg = &pll->reg_setup;



	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
@@ -336,7 +333,7 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) 
	u32 const delay_us = 100;

	u32 const timeout_us = 5000;



	rc = readl_poll_timeout_atomic(pll->mmio +

	rc = readl_poll_timeout_atomic(pll->phy->pll_base +

				       REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE,

				       status,

				       ((status & BIT(0)) > 0),
@@ -351,21 +348,21 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) 


static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll)

{

	u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);

	u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);



	dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);

	dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,

	dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);

	dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0,

		  data & ~BIT(5));

	ndelay(250);

}



static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll)

{

	u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);

	u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);



	dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,

	dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0,

		  data | BIT(5));

	dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);

	dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);

	ndelay(250);

}
@@ -373,8 +370,8 @@ static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll) 
{

	u32 data;



	data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);

	dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,

	data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);

	dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1,

		  data & ~BIT(5));

}
@@ -382,8 +379,8 @@ static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll) 
{

	u32 data;



	data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);

	dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,

	data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);

	dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1,

		  data | BIT(5));

}
@@ -404,7 +401,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) 
	}



	/* Start PLL */

	dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,

	dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,

		  0x01);



	/*
@@ -426,10 +423,10 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) 
	if (pll_10nm->slave)

		dsi_pll_enable_global_clk(pll_10nm->slave);



	dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL,

	dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL,

		  0x01);

	if (pll_10nm->slave)

		dsi_phy_write(pll_10nm->slave->phy_cmn_mmio +

		dsi_phy_write(pll_10nm->slave->phy->base +

			  REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01);



error:
@@ -438,7 +435,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) 


static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)

{

	dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);

	dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);

	dsi_pll_disable_pll_bias(pll);

}
@@ -452,7 +449,7 @@ static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw) 
	 * powering down the PLL

	 */

	dsi_pll_disable_global_clk(pll_10nm);

	dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0);

	dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0);

	dsi_pll_disable_sub(pll_10nm);

	if (pll_10nm->slave) {

		dsi_pll_disable_global_clk(pll_10nm->slave);
@@ -468,7 +465,7 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, 
{

	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);

	struct dsi_pll_config *config = &pll_10nm->pll_configuration;

	void __iomem *base = pll_10nm->mmio;

	void __iomem *base = pll_10nm->phy->pll_base;

	u64 ref_clk = pll_10nm->vco_ref_clk_rate;

	u64 vco_rate = 0x0;

	u64 multiplier;
@@ -531,10 +528,10 @@ static void dsi_10nm_pll_save_state(struct msm_dsi_phy *phy) 
{

	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);

	struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;

	void __iomem *phy_base = pll_10nm->phy_cmn_mmio;

	void __iomem *phy_base = pll_10nm->phy->base;

	u32 cmn_clk_cfg0, cmn_clk_cfg1;



	cached->pll_out_div = dsi_phy_read(pll_10nm->mmio +

	cached->pll_out_div = dsi_phy_read(pll_10nm->phy->pll_base +

				       REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);

	cached->pll_out_div &= 0x3;
@@ -554,14 +551,14 @@ static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy) 
{

	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);

	struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;

	void __iomem *phy_base = pll_10nm->phy_cmn_mmio;

	void __iomem *phy_base = pll_10nm->phy->base;

	u32 val;

	int ret;



	val = dsi_phy_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);

	val = dsi_phy_read(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);

	val &= ~0x3;

	val |= cached->pll_out_div;

	dsi_phy_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val);

	dsi_phy_write(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val);



	dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,

		  cached->bit_clk_div | (cached->pix_clk_div << 4));
@@ -588,7 +585,7 @@ static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy) 
static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)

{

	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);

	void __iomem *base = pll_10nm->phy_cmn_mmio;

	void __iomem *base = phy->base;

	u32 data = 0x0;	/* internal PLL */



	DBG("DSI PLL%d", pll_10nm->id);
@@ -647,7 +644,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 


	hw = devm_clk_hw_register_divider(dev, clk_name,

				     parent, CLK_SET_RATE_PARENT,

				     pll_10nm->mmio +

				     pll_10nm->phy->pll_base +

				     REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,

				     0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);

	if (IS_ERR(hw)) {
@@ -661,7 +658,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 
	/* BIT CLK: DIV_CTRL_3_0 */

	hw = devm_clk_hw_register_divider(dev, clk_name, parent,

				     CLK_SET_RATE_PARENT,

				     pll_10nm->phy_cmn_mmio +

				     pll_10nm->phy->base +

				     REG_DSI_10nm_PHY_CMN_CLK_CFG0,

				     0, 4, CLK_DIVIDER_ONE_BASED,

				     &pll_10nm->postdiv_lock);
@@ -712,7 +709,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 
	hw = devm_clk_hw_register_mux(dev, clk_name,

				 ((const char *[]){

				 parent, parent2, parent3, parent4

				 }), 4, 0, pll_10nm->phy_cmn_mmio +

				 }), 4, 0, pll_10nm->phy->base +

				 REG_DSI_10nm_PHY_CMN_CLK_CFG1,

				 0, 2, 0, NULL);

	if (IS_ERR(hw)) {
@@ -725,7 +722,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 


	/* PIX CLK DIV : DIV_CTRL_7_4*/

	hw = devm_clk_hw_register_divider(dev, clk_name, parent,

				     0, pll_10nm->phy_cmn_mmio +

				     0, pll_10nm->phy->base +

					REG_DSI_10nm_PHY_CMN_CLK_CFG0,

				     4, 4, CLK_DIVIDER_ONE_BASED,

				     &pll_10nm->postdiv_lock);
@@ -760,18 +757,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) 
	pll_10nm->id = id;

	pll_10nm_list[id] = pll_10nm;



	pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");

	if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {

		DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");

		return -ENOMEM;

	}



	pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");

	if (IS_ERR_OR_NULL(pll_10nm->mmio)) {

		DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");

		return -ENOMEM;

	}



	spin_lock_init(&pll_10nm->postdiv_lock);



	pll_10nm->phy = phy;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

+17 −32
Original line number Diff line number Diff line
@@ -118,9 +118,6 @@ struct dsi_pll_14nm { 
	int id;

	struct platform_device *pdev;



	void __iomem *phy_cmn_mmio;

	void __iomem *mmio;



	struct msm_dsi_phy *phy;



	struct dsi_pll_input in;
@@ -167,7 +164,7 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm, 
				    u32 nb_tries, u32 timeout_us)

{

	bool pll_locked = false;

	void __iomem *base = pll_14nm->mmio;

	void __iomem *base = pll_14nm->phy->pll_base;

	u32 tries, val;



	tries = nb_tries;
@@ -380,7 +377,7 @@ static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll) 


static void pll_db_commit_ssc(struct dsi_pll_14nm *pll)

{

	void __iomem *base = pll->mmio;

	void __iomem *base = pll->phy->pll_base;

	struct dsi_pll_input *pin = &pll->in;

	struct dsi_pll_output *pout = &pll->out;

	u8 data;
@@ -418,7 +415,7 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll, 
				 struct dsi_pll_input *pin,

				 struct dsi_pll_output *pout)

{

	void __iomem *base = pll->mmio;

	void __iomem *base = pll->phy->pll_base;

	u8 data;



	/* confgiure the non frequency dependent pll registers */
@@ -478,7 +475,7 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll, 


static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)

{

	void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;

	void __iomem *cmn_base = pll_14nm->phy->base;



	/* de assert pll start and apply pll sw reset */
@@ -497,8 +494,8 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, 
			       struct dsi_pll_input *pin,

			       struct dsi_pll_output *pout)

{

	void __iomem *base = pll->mmio;

	void __iomem *cmn_base = pll->phy_cmn_mmio;

	void __iomem *base = pll->phy->pll_base;

	void __iomem *cmn_base = pll->phy->base;

	u8 data;



	DBG("DSI%d PLL", pll->id);
@@ -614,7 +611,7 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, 
						  unsigned long parent_rate)

{

	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);

	void __iomem *base = pll_14nm->mmio;

	void __iomem *base = pll_14nm->phy->pll_base;

	u64 vco_rate, multiplier = BIT(20);

	u32 div_frac_start;

	u32 dec_start;
@@ -653,8 +650,8 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, 
static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)

{

	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);

	void __iomem *base = pll_14nm->mmio;

	void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;

	void __iomem *base = pll_14nm->phy->pll_base;

	void __iomem *cmn_base = pll_14nm->phy->base;

	bool locked;



	DBG("");
@@ -682,7 +679,7 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) 
static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)

{

	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);

	void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;

	void __iomem *cmn_base = pll_14nm->phy->base;



	DBG("");
@@ -724,7 +721,7 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw, 
{

	struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);

	struct dsi_pll_14nm *pll_14nm = postdiv->pll;

	void __iomem *base = pll_14nm->phy_cmn_mmio;

	void __iomem *base = pll_14nm->phy->base;

	u8 shift = postdiv->shift;

	u8 width = postdiv->width;

	u32 val;
@@ -757,7 +754,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 
{

	struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);

	struct dsi_pll_14nm *pll_14nm = postdiv->pll;

	void __iomem *base = pll_14nm->phy_cmn_mmio;

	void __iomem *base = pll_14nm->phy->base;

	spinlock_t *lock = &pll_14nm->postdiv_lock;

	u8 shift = postdiv->shift;

	u8 width = postdiv->width;
@@ -784,7 +781,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 
	 */

	if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {

		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;

		void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;

		void __iomem *slave_base = pll_14nm_slave->phy->base;



		dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);

	}
@@ -808,7 +805,7 @@ static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy) 
{

	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);

	struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;

	void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;

	void __iomem *cmn_base = pll_14nm->phy->base;

	u32 data;



	data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
@@ -826,7 +823,7 @@ static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy) 
{

	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);

	struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;

	void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;

	void __iomem *cmn_base = pll_14nm->phy->base;

	u32 data;

	int ret;
@@ -848,7 +845,7 @@ static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy) 
	/* also restore post-dividers for slave DSI PLL */

	if (phy->usecase == MSM_DSI_PHY_MASTER) {

		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;

		void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;

		void __iomem *slave_base = pll_14nm_slave->phy->base;



		dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);

	}
@@ -859,7 +856,7 @@ static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy) 
static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)

{

	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);

	void __iomem *base = pll_14nm->mmio;

	void __iomem *base = phy->pll_base;

	u32 clkbuflr_en, bandgap = 0;



	switch (phy->usecase) {
@@ -1011,18 +1008,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) 
	pll_14nm->id = id;

	pll_14nm_list[id] = pll_14nm;



	pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");

	if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {

		DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");

		return -ENOMEM;

	}



	pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");

	if (IS_ERR_OR_NULL(pll_14nm->mmio)) {

		DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");

		return -ENOMEM;

	}



	spin_lock_init(&pll_14nm->postdiv_lock);



	pll_14nm->phy = phy;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c

+12 −21
Original line number Diff line number Diff line
@@ -72,8 +72,6 @@ struct dsi_pll_28nm { 


	struct msm_dsi_phy *phy;



	void __iomem *mmio;



	struct pll_28nm_cached_state cached_state;

};
@@ -86,7 +84,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, 
	u32 val;



	while (nb_tries--) {

		val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS);

		val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS);

		pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY);



		if (pll_locked)
@@ -101,7 +99,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, 


static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm)

{

	void __iomem *base = pll_28nm->mmio;

	void __iomem *base = pll_28nm->phy->pll_base;



	/*

	 * Add HW recommended delays after toggling the software
@@ -120,7 +118,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, 
{

	struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);

	struct device *dev = &pll_28nm->pdev->dev;

	void __iomem *base = pll_28nm->mmio;

	void __iomem *base = pll_28nm->phy->pll_base;

	unsigned long div_fbx1000, gen_vco_clk;

	u32 refclk_cfg, frac_n_mode, frac_n_value;

	u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
@@ -244,7 +242,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, 
		unsigned long parent_rate)

{

	struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);

	void __iomem *base = pll_28nm->mmio;

	void __iomem *base = pll_28nm->phy->pll_base;

	u32 sdm0, doubler, sdm_byp_div;

	u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;

	u32 ref_clk = VCO_REF_CLK_RATE;
@@ -291,7 +289,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, 
static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm)

{

	struct device *dev = &pll_28nm->pdev->dev;

	void __iomem *base = pll_28nm->mmio;

	void __iomem *base = pll_28nm->phy->pll_base;

	u32 max_reads = 5, timeout_us = 100;

	bool locked;

	u32 val;
@@ -385,7 +383,7 @@ static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) 
{

	struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);

	struct device *dev = &pll_28nm->pdev->dev;

	void __iomem *base = pll_28nm->mmio;

	void __iomem *base = pll_28nm->phy->pll_base;

	bool locked;

	u32 max_reads = 10, timeout_us = 50;

	u32 val;
@@ -439,7 +437,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) 
	if (unlikely(!pll_28nm->phy->pll_on))

		return;



	dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);

	dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);



	pll_28nm->phy->pll_on = false;

}
@@ -483,7 +481,7 @@ static void dsi_28nm_pll_save_state(struct msm_dsi_phy *phy) 
{

	struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);

	struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;

	void __iomem *base = pll_28nm->mmio;

	void __iomem *base = pll_28nm->phy->pll_base;



	cached_state->postdiv3 =

			dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
@@ -500,7 +498,7 @@ static int dsi_28nm_pll_restore_state(struct msm_dsi_phy *phy) 
{

	struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);

	struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;

	void __iomem *base = pll_28nm->mmio;

	void __iomem *base = pll_28nm->phy->pll_base;

	int ret;



	ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
@@ -551,7 +549,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov 
	snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);

	hw = devm_clk_hw_register_divider(dev, clk_name,

			parent1, CLK_SET_RATE_PARENT,

			pll_28nm->mmio +

			pll_28nm->phy->pll_base +

			REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,

			0, 4, 0, NULL);

	if (IS_ERR(hw))
@@ -568,7 +566,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov 
	snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);

	snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);

	hw = devm_clk_hw_register_divider(dev, clk_name,

				parent1, 0, pll_28nm->mmio +

				parent1, 0, pll_28nm->phy->pll_base +

				REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,

				0, 8, 0, NULL);

	if (IS_ERR(hw))
@@ -581,7 +579,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov 
	hw = devm_clk_hw_register_mux(dev, clk_name,

			((const char *[]){

				parent1, parent2

			}), 2, CLK_SET_RATE_PARENT, pll_28nm->mmio +

			}), 2, CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base +

			REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL);

	if (IS_ERR(hw))

		return PTR_ERR(hw);
@@ -613,13 +611,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) 


	pll_28nm->pdev = pdev;

	pll_28nm->id = id;



	pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");

	if (IS_ERR_OR_NULL(pll_28nm->mmio)) {

		DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);

		return -ENOMEM;

	}



	pll_28nm->phy = phy;



	ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);