Commit b7b20cfe authored by Zhifeng Tang's avatar Zhifeng Tang Committed by Stephen Boyd
Browse files

clk: sprd: Fix thm_parents incorrect configuration 



The thm*_clk have two clock sources 32k and 250k,excluding 32m.

Fixes: af3bd365 ("clk: sprd: Add clocks support for UMS512")
Signed-off-by: default avatarZhifeng Tang <zhifeng.tang@unisoc.com>
Acked-by: default avatarChunyan Zhang <zhang.lyra@gmail.com>
Reviewed-by: default avatarBaolin Wang <baolin.wang@linux.alibaba.com>
Link: https://lore.kernel.org/r/20230824092624.20020-1-zhifeng.tang@unisoc.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent eec11486

drivers/clk/sprd/ums512-clk.c

+1 −1
Original line number Diff line number Diff line
@@ -800,7 +800,7 @@ static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents, 
			 0x250, 0, 3, UMS512_MUX_FLAG);



static const struct clk_parent_data thm_parents[] = {

	{ .fw_name = "ext-32m" },

	{ .fw_name = "ext-32k" },

	{ .hw = &clk_250k.hw  },

};

static SPRD_MUX_CLK_DATA(thm0_clk, "thm0-clk", thm_parents,