Commit b7aa2288 authored by Álvaro Fernández Rojas's avatar Álvaro Fernández Rojas Committed by Thomas Bogendoerfer
Browse files

mips: bmips: dts: add BCM63268 reset controller support 



BCM63268 SoCs have a reset controller for certain components.

Signed-off-by: default avatarÁlvaro Fernández Rojas <noltari@gmail.com>
Acked-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 7acf84e8

arch/mips/boot/dts/brcm/bcm63268.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -70,6 +70,12 @@ 
			mask = <0x1>;

		};



		periph_rst: reset-controller@10000010 {

			compatible = "brcm,bcm6345-reset";

			reg = <0x10000010 0x4>;

			#reset-cells = <1>;

		};



		periph_intc: interrupt-controller@10000020 {

			compatible = "brcm,bcm6345-l1-intc";

			reg = <0x10000020 0x20>,

include/dt-bindings/reset/bcm63268-reset.h

0 → 100644
+26 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0+ */



#ifndef __DT_BINDINGS_RESET_BCM63268_H

#define __DT_BINDINGS_RESET_BCM63268_H



#define BCM63268_RST_SPI	0

#define BCM63268_RST_IPSEC	1

#define BCM63268_RST_EPHY	2

#define BCM63268_RST_SAR	3

#define BCM63268_RST_ENETSW	4

#define BCM63268_RST_USBS	5

#define BCM63268_RST_USBH	6

#define BCM63268_RST_PCM	7

#define BCM63268_RST_PCIE_CORE	8

#define BCM63268_RST_PCIE	9

#define BCM63268_RST_PCIE_EXT	10

#define BCM63268_RST_WLAN_SHIM	11

#define BCM63268_RST_DDR_PHY	12

#define BCM63268_RST_FAP0	13

#define BCM63268_RST_WLAN_UBUS	14

#define BCM63268_RST_DECT	15

#define BCM63268_RST_FAP1	16

#define BCM63268_RST_PCIE_HARD	17

#define BCM63268_RST_GPHY	18



#endif /* __DT_BINDINGS_RESET_BCM63268_H */