Commit b71a4a25 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Clean up SSKPD/MLTR defines 



Give names to the SSKPD/MLTR fields, and use the
REG_GENMASK* and REG_FIELD_GET*.

Also drop the bogus non-mirrored SSKP register define.

v2: Rebase due to intel_mchbar_regs.h
    Leave gen6_check_mch_setup() in place for the moment

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220216232806.6194-3-ville.syrjala@linux.intel.com
parent 84073e56

drivers/gpu/drm/i915/i915_reg.h

+0 −8
Original line number Diff line number Diff line
@@ -4210,14 +4210,6 @@ 
	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \

	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))



/* the address where we get all kinds of latency value */

#define SSKPD			_MMIO(0x5d10)

#define SSKPD_WM_MASK		0x3f

#define SSKPD_WM0_SHIFT		0

#define SSKPD_WM1_SHIFT		8

#define SSKPD_WM2_SHIFT		16

#define SSKPD_WM3_SHIFT		24



/*

 * The two pipe frame counter registers are not synchronized, so

 * reading a stable value is somewhat tricky. The following code

drivers/gpu/drm/i915/intel_mchbar_regs.h

+12 −5
Original line number Diff line number Diff line
@@ -78,10 +78,9 @@ 


/* Memory latency timer register */

#define MLTR_ILK				_MMIO(MCHBAR_MIRROR_BASE + 0x1222)

#define   MLTR_WM1_SHIFT			0

#define   MLTR_WM2_SHIFT			8

/* the unit of memory self-refresh latency time is 0.5us */

#define   ILK_SRLT_MASK				0x3f

#define   MLTR_WM2_MASK				REG_GENMASK(13, 8)

#define   MLTR_WM1_MASK				REG_GENMASK(5, 0)



#define CSIPLL0					_MMIO(MCHBAR_MIRROR_BASE + 0x2c10)

#define DDRMPLL1				_MMIO(MCHBAR_MIRROR_BASE + 0x2c20)
@@ -199,8 +198,16 @@ 


/* snb MCH registers for priority tuning */

#define MCH_SSKPD				_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)

#define   MCH_SSKPD_WM0_MASK			0x3f

#define   MCH_SSKPD_WM0_VAL			0xc

#define   SSKPD_NEW_WM0_MASK_HSW		REG_GENMASK64(63, 56)

#define   SSKPD_WM4_MASK_HSW			REG_GENMASK64(40, 32)

#define   SSKPD_WM3_MASK_HSW			REG_GENMASK64(28, 20)

#define   SSKPD_WM2_MASK_HSW			REG_GENMASK64(19, 12)

#define   SSKPD_WM1_MASK_HSW			REG_GENMASK64(11, 4)

#define   SSKPD_OLD_WM0_MASK_HSW		REG_GENMASK64(3, 0)

#define   SSKPD_WM3_MASK_SNB			REG_GENMASK(29, 24)

#define   SSKPD_WM2_MASK_SNB			REG_GENMASK(21, 16)

#define   SSKPD_WM1_MASK_SNB			REG_GENMASK(13, 8)

#define   SSKPD_WM0_MASK_SNB			REG_GENMASK(5, 0)



/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */

#define DCLK					_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)

drivers/gpu/drm/i915/intel_pm.c

+13 −13
Original line number Diff line number Diff line
@@ -2947,27 +2947,27 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, 
	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {

		u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);



		wm[0] = (sskpd >> 56) & 0xFF;

		wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);

		if (wm[0] == 0)

			wm[0] = sskpd & 0xF;

		wm[1] = (sskpd >> 4) & 0xFF;

		wm[2] = (sskpd >> 12) & 0xFF;

		wm[3] = (sskpd >> 20) & 0x1FF;

		wm[4] = (sskpd >> 32) & 0x1FF;

			wm[0] = REG_FIELD_GET64(SSKPD_OLD_WM0_MASK_HSW, sskpd);

		wm[1] = REG_FIELD_GET64(SSKPD_WM1_MASK_HSW, sskpd);

		wm[2] = REG_FIELD_GET64(SSKPD_WM2_MASK_HSW, sskpd);

		wm[3] = REG_FIELD_GET64(SSKPD_WM3_MASK_HSW, sskpd);

		wm[4] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd);

	} else if (DISPLAY_VER(dev_priv) >= 6) {

		u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);



		wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;

		wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;

		wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;

		wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;

		wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);

		wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);

		wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);

		wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);

	} else if (DISPLAY_VER(dev_priv) >= 5) {

		u32 mltr = intel_uncore_read(uncore, MLTR_ILK);



		/* ILK primary LP0 latency is 700 ns */

		wm[0] = 7;

		wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;

		wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;

		wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr);

		wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);

	} else {

		MISSING_CASE(INTEL_DEVID(dev_priv));

	}
@@ -7394,7 +7394,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *dev_priv) 
	u32 tmp;



	tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);

	if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)

	if (REG_FIELD_GET(SSKPD_WM0_MASK_SNB, tmp) != 12)

		drm_dbg_kms(&dev_priv->drm,

			    "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",

			    tmp);