Commit b6c81be9 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Lorenzo Pieralisi
Browse files

dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument 

Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
argument. The argument is the register offset within "syscon" used to
configure PCIe controller. This change is as discussed in [1]

[1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com

Link: https://lore.kernel.org/r/20201210124917.24185-2-kishon@ti.com


Fixes: 431b53b8 ("dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC")
Fixes: 45b39e92 ("dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC")
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
parent e87d17ca

Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml

+7 −4
Original line number Diff line number Diff line
@@ -29,9 +29,12 @@ properties: 
      - const: mem



  ti,syscon-pcie-ctrl:

    description: Phandle to the SYSCON entry required for configuring PCIe mode

                 and link speed.

    $ref: /schemas/types.yaml#/definitions/phandle

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: Phandle to the SYSCON entry

          - description: pcie_ctrl register offset within SYSCON

    description: Specifier for configuring PCIe mode and link speed.



  power-domains:

    maxItems: 1
@@ -79,7 +82,7 @@ examples: 
                 <0x00 0x0d000000 0x00 0x00800000>,

                 <0x00 0x10000000 0x00 0x08000000>;

           reg-names = "intd_cfg", "user_cfg", "reg", "mem";

           ti,syscon-pcie-ctrl = <&pcie0_ctrl>;

           ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;

           max-link-speed = <3>;

           num-lanes = <2>;

           power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;

Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml

+7 −4
Original line number Diff line number Diff line
@@ -29,9 +29,12 @@ properties: 
      - const: cfg



  ti,syscon-pcie-ctrl:

    description: Phandle to the SYSCON entry required for configuring PCIe mode

      and link speed.

    $ref: /schemas/types.yaml#/definitions/phandle

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: Phandle to the SYSCON entry

          - description: pcie_ctrl register offset within SYSCON

    description: Specifier for configuring PCIe mode and link speed.



  power-domains:

    maxItems: 1
@@ -90,7 +93,7 @@ examples: 
                  <0x00 0x0d000000 0x00 0x00800000>,

                  <0x00 0x10000000 0x00 0x00001000>;

            reg-names = "intd_cfg", "user_cfg", "reg", "cfg";

            ti,syscon-pcie-ctrl = <&pcie0_ctrl>;

            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;

            max-link-speed = <3>;

            num-lanes = <2>;

            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;