Commit b691505e authored by Jordan Niethe's avatar Jordan Niethe Committed by Michael Ellerman
Browse files

powerpc: Define new SRR1 bits for a ISA v3.1 



Add the BOUNDARY SRR1 bit definition for when the cause of an
alignment exception is a prefixed instruction that crosses a 64-byte
boundary. Add the PREFIXED SRR1 bit definition for exceptions caused
by prefixed instructions.

Bit 35 of SRR1 is called SRR1_ISI_N_OR_G. This name comes from it
being used to indicate that an ISI was due to the access being no-exec
or guarded. ISA v3.1 adds another purpose. It is also set if there is
an access in a cache-inhibited location for prefixed instruction.
Rename from SRR1_ISI_N_OR_G to SRR1_ISI_N_G_OR_CIP.

Signed-off-by: default avatarJordan Niethe <jniethe5@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Reviewed-by: default avatarAlistair Popple <alistair@popple.id.au>
Link: https://lore.kernel.org/r/20200506034050.24806-23-jniethe5@gmail.com
parent 2aa6195e

arch/powerpc/include/asm/reg.h

+3 −1
Original line number Diff line number Diff line
@@ -762,7 +762,7 @@ 
#endif



#define   SRR1_ISI_NOPT		0x40000000 /* ISI: Not found in hash */

#define   SRR1_ISI_N_OR_G	0x10000000 /* ISI: Access is no-exec or G */

#define   SRR1_ISI_N_G_OR_CIP	0x10000000 /* ISI: Access is no-exec or G or CI for a prefixed instruction */

#define   SRR1_ISI_PROT		0x08000000 /* ISI: Other protection fault */

#define   SRR1_WAKEMASK		0x00380000 /* reason for wakeup */

#define   SRR1_WAKEMASK_P8	0x003c0000 /* reason for wakeup on POWER8 and 9 */
@@ -789,6 +789,8 @@ 
#define   SRR1_PROGADDR		0x00010000 /* SRR0 contains subsequent addr */



#define   SRR1_MCE_MCP		0x00080000 /* Machine check signal caused interrupt */

#define   SRR1_BOUNDARY		0x10000000 /* Prefixed instruction crosses 64-byte boundary */

#define   SRR1_PREFIXED		0x20000000 /* Exception caused by prefixed instruction */



#define SPRN_HSRR0	0x13A	/* Save/Restore Register 0 */

#define SPRN_HSRR1	0x13B	/* Save/Restore Register 1 */

arch/powerpc/kvm/book3s_hv_nested.c

+1 −1
Original line number Diff line number Diff line
@@ -1182,7 +1182,7 @@ static int kvmhv_translate_addr_nested(struct kvm_vcpu *vcpu, 
		} else if (vcpu->arch.trap == BOOK3S_INTERRUPT_H_INST_STORAGE) {

			/* Can we execute? */

			if (!gpte_p->may_execute) {

				flags |= SRR1_ISI_N_OR_G;

				flags |= SRR1_ISI_N_G_OR_CIP;

				goto forward_to_l1;

			}

		} else {

arch/powerpc/kvm/book3s_hv_rm_mmu.c

+1 −1
Original line number Diff line number Diff line
@@ -1240,7 +1240,7 @@ long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned long addr, 
	status &= ~DSISR_NOHPTE;	/* DSISR_NOHPTE == SRR1_ISI_NOPT */

	if (!data) {

		if (gr & (HPTE_R_N | HPTE_R_G))

			return status | SRR1_ISI_N_OR_G;

			return status | SRR1_ISI_N_G_OR_CIP;

		if (!hpte_read_permission(pp, slb_v & key))

			return status | SRR1_ISI_PROT;

	} else if (status & DSISR_ISSTORE) {