Commit b67ab6fb authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Joerg Roedel
Browse files

dt-bindings: iommu: renesas, ipmmu-vmsa: Update for R-Car Gen4 



Since R-Car Gen4 does not have the main IPMMU IMSSTR register, update
the bindings to drop the interrupt bit number from the
renesas,ipmmu-main property.

Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[geert: Re-add removed items level, add minItems/maxItems constraints]
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230313124026.954514-1-yoshihiro.shimoda.uh@renesas.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent efe37fda

Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml

+24 −8
Original line number Original line Diff line number Diff line
@@ -74,16 +74,16 @@ properties: 
  renesas,ipmmu-main:

  renesas,ipmmu-main:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

    items:

      - items:

      - minItems: 1

        items:

          - description: phandle to main IPMMU

          - description: phandle to main IPMMU

          - description: the interrupt bit number associated with the particular

          - description:

              cache IPMMU device. The interrupt bit number needs to match the main

              The interrupt bit number associated with the particular cache

              IPMMU IMSSTR register. Only used by cache IPMMU instances.

              IPMMU device. If present, the interrupt bit number needs to match

              the main IPMMU IMSSTR register. Only used by cache IPMMU

              instances.

    description:

    description:

      Reference to the main IPMMU phandle plus 1 cell. The cell is

      Reference to the main IPMMU.

      the interrupt bit number associated with the particular cache IPMMU

      device. The interrupt bit number needs to match the main IPMMU IMSSTR

      register. Only used by cache IPMMU instances.





required:

required:

  - compatible

  - compatible
@@ -109,6 +109,22 @@ allOf: 
      required:

      required:

        - power-domains

        - power-domains





  - if:

      properties:

        compatible:

          contains:

            const: renesas,rcar-gen4-ipmmu-vmsa

    then:

      properties:

        renesas,ipmmu-main:

          items:

            - maxItems: 1

    else:

      properties:

        renesas,ipmmu-main:

          items:

            - minItems: 2



examples:

examples:

  - |

  - |

    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>

    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>