Commit b6740089 authored by Chanho Park's avatar Chanho Park Committed by Krzysztof Kozlowski
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dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 



There are duplicated definitions of peric0 and peric1 cmu blocks. Thus,
they should be defined correctly as numerical order.

Fixes: 680e1c83 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9")
Signed-off-by: default avatarChanho Park <chanho61.park@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220727021357.152421-2-chanho61.park@samsung.com
parent 568035b0

include/dt-bindings/clock/samsung,exynosautov9.h

+28 −28
Original line number Diff line number Diff line
@@ -226,21 +226,21 @@ 
#define CLK_GOUT_PERIC0_IPCLK_8		28

#define CLK_GOUT_PERIC0_IPCLK_9		29

#define CLK_GOUT_PERIC0_IPCLK_10	30

#define CLK_GOUT_PERIC0_IPCLK_11	30

#define CLK_GOUT_PERIC0_PCLK_0		31

#define CLK_GOUT_PERIC0_PCLK_1		32

#define CLK_GOUT_PERIC0_PCLK_2		33

#define CLK_GOUT_PERIC0_PCLK_3		34

#define CLK_GOUT_PERIC0_PCLK_4		35

#define CLK_GOUT_PERIC0_PCLK_5		36

#define CLK_GOUT_PERIC0_PCLK_6		37

#define CLK_GOUT_PERIC0_PCLK_7		38

#define CLK_GOUT_PERIC0_PCLK_8		39

#define CLK_GOUT_PERIC0_PCLK_9		40

#define CLK_GOUT_PERIC0_PCLK_10		41

#define CLK_GOUT_PERIC0_PCLK_11		42

#define CLK_GOUT_PERIC0_IPCLK_11	31

#define CLK_GOUT_PERIC0_PCLK_0		32

#define CLK_GOUT_PERIC0_PCLK_1		33

#define CLK_GOUT_PERIC0_PCLK_2		34

#define CLK_GOUT_PERIC0_PCLK_3		35

#define CLK_GOUT_PERIC0_PCLK_4		36

#define CLK_GOUT_PERIC0_PCLK_5		37

#define CLK_GOUT_PERIC0_PCLK_6		38

#define CLK_GOUT_PERIC0_PCLK_7		39

#define CLK_GOUT_PERIC0_PCLK_8		40

#define CLK_GOUT_PERIC0_PCLK_9		41

#define CLK_GOUT_PERIC0_PCLK_10		42

#define CLK_GOUT_PERIC0_PCLK_11		43



#define PERIC0_NR_CLK			43

#define PERIC0_NR_CLK			44



/* CMU_PERIC1 */

#define CLK_MOUT_PERIC1_BUS_USER	1
@@ -272,21 +272,21 @@ 
#define CLK_GOUT_PERIC1_IPCLK_8		28

#define CLK_GOUT_PERIC1_IPCLK_9		29

#define CLK_GOUT_PERIC1_IPCLK_10	30

#define CLK_GOUT_PERIC1_IPCLK_11	30

#define CLK_GOUT_PERIC1_PCLK_0		31

#define CLK_GOUT_PERIC1_PCLK_1		32

#define CLK_GOUT_PERIC1_PCLK_2		33

#define CLK_GOUT_PERIC1_PCLK_3		34

#define CLK_GOUT_PERIC1_PCLK_4		35

#define CLK_GOUT_PERIC1_PCLK_5		36

#define CLK_GOUT_PERIC1_PCLK_6		37

#define CLK_GOUT_PERIC1_PCLK_7		38

#define CLK_GOUT_PERIC1_PCLK_8		39

#define CLK_GOUT_PERIC1_PCLK_9		40

#define CLK_GOUT_PERIC1_PCLK_10		41

#define CLK_GOUT_PERIC1_PCLK_11		42

#define CLK_GOUT_PERIC1_IPCLK_11	31

#define CLK_GOUT_PERIC1_PCLK_0		32

#define CLK_GOUT_PERIC1_PCLK_1		33

#define CLK_GOUT_PERIC1_PCLK_2		34

#define CLK_GOUT_PERIC1_PCLK_3		35

#define CLK_GOUT_PERIC1_PCLK_4		36

#define CLK_GOUT_PERIC1_PCLK_5		37

#define CLK_GOUT_PERIC1_PCLK_6		38

#define CLK_GOUT_PERIC1_PCLK_7		39

#define CLK_GOUT_PERIC1_PCLK_8		40

#define CLK_GOUT_PERIC1_PCLK_9		41

#define CLK_GOUT_PERIC1_PCLK_10		42

#define CLK_GOUT_PERIC1_PCLK_11		43



#define PERIC1_NR_CLK			43

#define PERIC1_NR_CLK			44



/* CMU_PERIS */

#define CLK_MOUT_PERIS_BUS_USER		1