Commit b6065ebf authored by Ruijing Dong's avatar Ruijing Dong Committed by Alex Deucher
Browse files

drm/amdgpu/vcn: Update fw shared data structure 



Add fw log in fw shared data structure.

Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarRuijing Dong <ruijing.dong@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 811c04db

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

+9 −5
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 
	const char *fw_name;

	const struct common_firmware_header *hdr;

	unsigned char fw_check;

	unsigned int fw_shared_size;

	int i, r;



	INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
@@ -226,7 +227,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 
	bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;

	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)

		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);

	bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));

	fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));

	bo_size += fw_shared_size;



	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {

		if (adev->vcn.harvest_config & (1 << i))
@@ -240,10 +242,12 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 
			return r;

		}



		adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr +

				bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));

		adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr +

				bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));

		adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +

				bo_size - fw_shared_size;

		adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +

				bo_size - fw_shared_size;



		adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;



		if (adev->vcn.indirect_sram) {

			r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+24 −2
Original line number Diff line number Diff line
@@ -205,6 +205,13 @@ struct amdgpu_vcn_reg{ 
	unsigned	scratch9;

};



struct amdgpu_vcn_fw_shared {

	void        *cpu_addr;

	uint64_t    gpu_addr;

	uint32_t    mem_size;

	uint32_t    log_offset;

};



struct amdgpu_vcn_inst {

	struct amdgpu_bo	*vcpu_bo;

	void			*cpu_addr;
@@ -221,8 +228,7 @@ struct amdgpu_vcn_inst { 
	uint64_t		dpg_sram_gpu_addr;

	uint32_t		*dpg_sram_curr_addr;

	atomic_t		dpg_enc_submission_cnt;

	void			*fw_shared_cpu_addr;

	uint64_t		fw_shared_gpu_addr;

	struct amdgpu_vcn_fw_shared fw_shared;

};



struct amdgpu_vcn {
@@ -265,6 +271,13 @@ struct amdgpu_fw_shared_sw_ring { 
	uint8_t padding[3];

};



struct amdgpu_fw_shared_fw_logging {

	uint8_t is_enabled;

	uint32_t addr_lo;

	uint32_t addr_hi;

	uint32_t size;

};



struct amdgpu_fw_shared {

	uint32_t present_flag_0;

	uint8_t pad[44];
@@ -272,6 +285,15 @@ struct amdgpu_fw_shared { 
	uint8_t pad1[1];

	struct amdgpu_fw_shared_multi_queue multi_queue;

	struct amdgpu_fw_shared_sw_ring sw_ring;

	struct amdgpu_fw_shared_fw_logging fw_log;

};



struct amdgpu_vcn_fwlog {

	uint32_t rptr;

	uint32_t wptr;

	uint32_t buffer_size;

	uint32_t header_size;

	uint8_t wrapped;

};



struct amdgpu_vcn_decode_buffer {

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

+9 −9
Original line number Diff line number Diff line
@@ -172,7 +172,7 @@ static int vcn_v2_0_sw_init(void *handle) 
	if (r)

		return r;



	fw_shared = adev->vcn.inst->fw_shared_cpu_addr;

	fw_shared = adev->vcn.inst->fw_shared.cpu_addr;

	fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);

	return 0;

}
@@ -188,7 +188,7 @@ static int vcn_v2_0_sw_fini(void *handle) 
{

	int r, idx;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;

	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;



	if (drm_dev_enter(adev_to_drm(adev), &idx)) {

		fw_shared->present_flag_0 = 0;
@@ -364,9 +364,9 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev) 


	/* non-cache window */

	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,

		lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr));

		lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr));

	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,

		upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr));

		upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr));

	WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0);

	WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0,

		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
@@ -455,10 +455,10 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec 
	/* non-cache window */

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),

		lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect);

		lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),

		upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect);

		upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
@@ -784,7 +784,7 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev) 


static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)

{

	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;

	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;

	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;

	uint32_t rb_bufsz, tmp;
@@ -921,7 +921,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) 


static int vcn_v2_0_start(struct amdgpu_device *adev)

{

	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;

	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;

	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;

	uint32_t rb_bufsz, tmp;

	uint32_t lmi_swap_cntl;
@@ -1207,7 +1207,7 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 
				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);



			if (!ret_code) {

				volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;

				volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;

				/* pause DPG */

				reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

				WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

+9 −9
Original line number Diff line number Diff line
@@ -196,7 +196,7 @@ static int vcn_v2_5_sw_init(void *handle) 
				return r;

		}



		fw_shared = adev->vcn.inst[j].fw_shared_cpu_addr;

		fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr;

		fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);

	}
@@ -229,7 +229,7 @@ static int vcn_v2_5_sw_fini(void *handle) 
		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {

			if (adev->vcn.harvest_config & (1 << i))

				continue;

			fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;

			fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

			fw_shared->present_flag_0 = 0;

		}

		drm_dev_exit(idx);
@@ -423,9 +423,9 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev) 


		/* non-cache window */

		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,

			lower_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr));

			lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));

		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,

			upper_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr));

			upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));

		WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0);

		WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0,

			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
@@ -513,10 +513,10 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx 
	/* non-cache window */

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),

		lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);

		lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),

		upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);

		upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
@@ -757,7 +757,7 @@ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev) 


static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)

{

	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;

	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

	struct amdgpu_ring *ring;

	uint32_t rb_bufsz, tmp;
@@ -981,7 +981,7 @@ static int vcn_v2_5_start(struct amdgpu_device *adev) 
	vcn_v2_5_mc_resume(adev);



	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {

		volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;

		volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

		if (adev->vcn.harvest_config & (1 << i))

			continue;

		/* VCN global tiling registers */
@@ -1403,7 +1403,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 
				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);



			if (!ret_code) {

				volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;

				volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;



				/* pause DPG */

				reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+10 −10
Original line number Diff line number Diff line
@@ -213,7 +213,7 @@ static int vcn_v3_0_sw_init(void *handle) 
				return r;

		}



		fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;

		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

		fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |

					     cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |

					     cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
@@ -249,7 +249,7 @@ static int vcn_v3_0_sw_fini(void *handle) 


			if (adev->vcn.harvest_config & (1 << i))

				continue;

			fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;

			fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

			fw_shared->present_flag_0 = 0;

			fw_shared->sw_ring.is_enabled = false;

		}
@@ -469,9 +469,9 @@ static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 


	/* non-cache window */

	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,

		lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));

		lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,

		upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));

		upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

	WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);

	WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,

		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
@@ -558,10 +558,10 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx 
	/* non-cache window */

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),

			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);

			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),

			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);

			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
@@ -923,7 +923,7 @@ static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 


static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)

{

	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;

	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

	struct amdgpu_ring *ring;

	uint32_t rb_bufsz, tmp;
@@ -1220,7 +1220,7 @@ static int vcn_v3_0_start(struct amdgpu_device *adev) 
		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);



		fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;

		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

		fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);



		/* programm the RB_BASE for ring buffer */
@@ -1611,7 +1611,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 


				if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {

					/* Restore */

					fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;

					fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

					fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);

					ring = &adev->vcn.inst[inst_idx].ring_enc[0];

					ring->wptr = 0;
@@ -1700,7 +1700,7 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 


	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {

		/*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */

		fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr;

		fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr;

		fw_shared->rb.wptr = lower_32_bits(ring->wptr);

		WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,

			lower_32_bits(ring->wptr));