Commit b5ce6fe8 authored by Josip Pavic's avatar Josip Pavic Committed by Alex Deucher
Browse files

drm/amd/display: add missing ABM register offsets 



[Why]
Some ABM registers don't exist on DCN 3.01, so are
missing from its register offset list. However,
this list was copied to later versions of DCN that
do have these registers. As a result, they're
inaccessible from the driver on those DCN versions
even though they exist.

[How]
Add the missing ABM register offsets to DCN 3.02+

Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarJosip Pavic <Josip.Pavic@amd.com>
Tested-by: default avatarDaniel Wheeler <Daniel.Wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f01ee019

drivers/gpu/drm/amd/display/dc/dce/dce_abm.h

+16 −0
Original line number Diff line number Diff line
@@ -96,6 +96,22 @@ 
	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \

	NBIO_SR(BIOS_SCRATCH_2)



#define ABM_DCN302_REG_LIST(id)\

	ABM_COMMON_REG_LIST_DCE_BASE(), \

	SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \

	SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \

	SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \

	SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \

	SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \

	SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \

	SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \

	SRI(BL1_PWM_USER_LEVEL, ABM, id), \

	SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \

	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \

	SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \

	SRI(DC_ABM1_ACE_THRES_12, ABM, id), \

	NBIO_SR(BIOS_SCRATCH_2)



#define ABM_DCN30_REG_LIST(id)\

	ABM_COMMON_REG_LIST_DCE_BASE(), \

	SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \

drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -1462,7 +1462,7 @@ static const struct dccg_mask dccg_mask = { 
};



#define abm_regs(id)\

		[id] = { ABM_DCN301_REG_LIST(id) }

		[id] = { ABM_DCN302_REG_LIST(id) }



static const struct dce_abm_registers abm_regs[] = {

		abm_regs(0),

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -1394,7 +1394,7 @@ static const struct dccg_mask dccg_mask = { 
};



#define abm_regs(id)\

		[id] = { ABM_DCN301_REG_LIST(id) }

		[id] = { ABM_DCN302_REG_LIST(id) }



static const struct dce_abm_registers abm_regs[] = {

		abm_regs(0),

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -366,7 +366,7 @@ static const struct dce110_clk_src_mask cs_mask = { 


#define abm_regs(id)\

[id] = {\

		ABM_DCN301_REG_LIST(id)\

		ABM_DCN302_REG_LIST(id)\

}



static const struct dce_abm_registers abm_regs[] = {