Commit b5ad2c21 authored Jan 15, 2015 by Markos Chandras

MIPS: mm: scache: Add secondary cache support for MIPS R6 cores



The secondary cache initialization and configuration code is processor
specific so we need to handle MIPS R6 cores as well.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

parent 4ee48627

arch/mips/mm/c-r4k.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -1473,7 +1473,8 @@ static void setup_scache(void)

		default:
		if (c->isa_level & (MIPS_CPU_ISA_M32R1 \| MIPS_CPU_ISA_M32R2 \|
		MIPS_CPU_ISA_M64R1 \| MIPS_CPU_ISA_M64R2)) {
		MIPS_CPU_ISA_M32R6 \| MIPS_CPU_ISA_M64R1 \|
		MIPS_CPU_ISA_M64R2 \| MIPS_CPU_ISA_M64R6)) {
		#ifdef CONFIG_MIPS_CPU_SCACHE
		if (mips_sc_init ()) {
		scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;

arch/mips/mm/sc-mips.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -105,7 +105,8 @@ static inline int __init mips_sc_probe(void)

		/* Ignore anything but MIPSxx processors */
		if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 \| MIPS_CPU_ISA_M32R2 \|
		MIPS_CPU_ISA_M64R1 \| MIPS_CPU_ISA_M64R2)))
		MIPS_CPU_ISA_M32R6 \| MIPS_CPU_ISA_M64R1 \|
		MIPS_CPU_ISA_M64R2 \| MIPS_CPU_ISA_M64R6)))
		return 0;

		/* Does this MIPS32/MIPS64 CPU have a config2 register? */