Commit b56e1cc4 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v5.12-rockchip-clk1' of... 

Merge tag 'v5.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - Kerneldoc fixes
 - some new rk3368 clock ids related to camera input

* tag 'v5.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix DPHY gate locations on rk3368
  clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368
  clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368
  clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
  clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
  clk: rockchip: Demote non-conformant kernel-doc header in half-divider
  clk: rockchip: Demote kernel-doc abuses to standard comment blocks in plls
  clk: rockchip: Remove unused/undocumented struct members from clk-cpu
  clk: rockchip: Demote non-conformant kernel-doc headers in main clock code
parents 5c8fe583 4bc23b3c

drivers/clk/rockchip/clk-cpu.c

+0 −4
Original line number Diff line number Diff line
@@ -51,10 +51,6 @@ 
 */

struct rockchip_cpuclk {

	struct clk_hw				hw;



	struct clk_mux				cpu_mux;

	const struct clk_ops			*cpu_mux_ops;



	struct clk				*alt_parent;

	void __iomem				*reg_base;

	struct notifier_block			clk_nb;

drivers/clk/rockchip/clk-half-divider.c

+1 −1
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ static const struct clk_ops clk_half_divider_ops = { 
	.set_rate = clk_half_divider_set_rate,

};



/**

/*

 * Register a clock branch.

 * Most clock branches have a form like

 *

drivers/clk/rockchip/clk-pll.c

+3 −3
Original line number Diff line number Diff line
@@ -97,7 +97,7 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) 
	return ret;

}



/**

/*

 * PLL used in RK3036

 */
@@ -358,7 +358,7 @@ static const struct clk_ops rockchip_rk3036_pll_clk_ops = { 
	.init = rockchip_rk3036_pll_init,

};



/**

/*

 * PLL used in RK3066, RK3188 and RK3288

 */
@@ -577,7 +577,7 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = { 
	.init = rockchip_rk3066_pll_init,

};



/**

/*

 * PLL used in RK3399

 */

drivers/clk/rockchip/clk-rk3368.c

+3 −3
Original line number Diff line number Diff line
@@ -474,7 +474,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { 
	COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,

			RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,

			RK3368_CLKGATE_CON(4), 5, GFLAGS),

	COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,

	COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,

			RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),



	COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
@@ -818,8 +818,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { 
	 * pclk_vio gates

	 * pclk_vio comes from the exactly same source as hclk_vio

	 */

	GATE(0, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),

	GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),

	GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 11, GFLAGS),

	GATE(PCLK_DPHYTX0, "pclk_dphytx0", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 10, GFLAGS),



	/* pclk_pd_pmu gates */

	GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),

drivers/clk/rockchip/clk.c

+2 −2
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ 
#include <linux/rational.h>

#include "clk.h"



/**

/*

 * Register a clock branch.

 * Most clock branches have a form like

 *
@@ -170,7 +170,7 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb, 
	return notifier_from_errno(ret);

}



/**

/*

 * fractional divider must set that denominator is 20 times larger than

 * numerator to generate precise clock frequency.

 */