Commit b5396271 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-riscv-6.5-1' of https://github.com/kvm-riscv/linux into HEAD 

KVM/riscv changes for 6.5

- Redirect AMO load/store misaligned traps to KVM guest
- Trap-n-emulate AIA in-kernel irqchip for KVM guest
- Svnapot support for KVM Guest
parents a443e260 07f225b5

arch/riscv/include/asm/csr.h

+2 −0
Original line number Diff line number Diff line
@@ -82,7 +82,9 @@ 
#define EXC_INST_ACCESS		1

#define EXC_INST_ILLEGAL	2

#define EXC_BREAKPOINT		3

#define EXC_LOAD_MISALIGNED	4

#define EXC_LOAD_ACCESS		5

#define EXC_STORE_MISALIGNED	6

#define EXC_STORE_ACCESS	7

#define EXC_SYSCALL		8

#define EXC_HYPERVISOR_SYSCALL	9

arch/riscv/include/asm/kvm_aia.h

+77 −30
Original line number Diff line number Diff line
@@ -20,6 +20,33 @@ struct kvm_aia { 


	/* In-kernel irqchip initialized */

	bool		initialized;



	/* Virtualization mode (Emulation, HW Accelerated, or Auto) */

	u32		mode;



	/* Number of MSIs */

	u32		nr_ids;



	/* Number of wired IRQs */

	u32		nr_sources;



	/* Number of group bits in IMSIC address */

	u32		nr_group_bits;



	/* Position of group bits in IMSIC address */

	u32		nr_group_shift;



	/* Number of hart bits in IMSIC address */

	u32		nr_hart_bits;



	/* Number of guest bits in IMSIC address */

	u32		nr_guest_bits;



	/* Guest physical address of APLIC */

	gpa_t		aplic_addr;



	/* Internal state of APLIC */

	void		*aplic_state;

};



struct kvm_vcpu_aia_csr {
@@ -38,25 +65,53 @@ struct kvm_vcpu_aia { 


	/* CPU AIA CSR context upon Guest VCPU reset */

	struct kvm_vcpu_aia_csr guest_reset_csr;



	/* Guest physical address of IMSIC for this VCPU */

	gpa_t		imsic_addr;



	/* HART index of IMSIC extacted from guest physical address */

	u32		hart_index;



	/* Internal state of IMSIC for this VCPU */

	void		*imsic_state;

};



#define KVM_RISCV_AIA_UNDEF_ADDR	(-1)



#define kvm_riscv_aia_initialized(k)	((k)->arch.aia.initialized)



#define irqchip_in_kernel(k)		((k)->arch.aia.in_kernel)



extern unsigned int kvm_riscv_aia_nr_hgei;

extern unsigned int kvm_riscv_aia_max_ids;

DECLARE_STATIC_KEY_FALSE(kvm_riscv_aia_available);

#define kvm_riscv_aia_available() \

	static_branch_unlikely(&kvm_riscv_aia_available)



extern struct kvm_device_ops kvm_riscv_aia_device_ops;



void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu *vcpu);

int kvm_riscv_vcpu_aia_imsic_update(struct kvm_vcpu *vcpu);



#define KVM_RISCV_AIA_IMSIC_TOPEI	(ISELECT_MASK + 1)

static inline int kvm_riscv_vcpu_aia_imsic_rmw(struct kvm_vcpu *vcpu,

					       unsigned long isel,

					       unsigned long *val,

					       unsigned long new_val,

					       unsigned long wr_mask)

{

	return 0;

}

int kvm_riscv_vcpu_aia_imsic_rmw(struct kvm_vcpu *vcpu, unsigned long isel,

				 unsigned long *val, unsigned long new_val,

				 unsigned long wr_mask);

int kvm_riscv_aia_imsic_rw_attr(struct kvm *kvm, unsigned long type,

				bool write, unsigned long *val);

int kvm_riscv_aia_imsic_has_attr(struct kvm *kvm, unsigned long type);

void kvm_riscv_vcpu_aia_imsic_reset(struct kvm_vcpu *vcpu);

int kvm_riscv_vcpu_aia_imsic_inject(struct kvm_vcpu *vcpu,

				    u32 guest_index, u32 offset, u32 iid);

int kvm_riscv_vcpu_aia_imsic_init(struct kvm_vcpu *vcpu);

void kvm_riscv_vcpu_aia_imsic_cleanup(struct kvm_vcpu *vcpu);



int kvm_riscv_aia_aplic_set_attr(struct kvm *kvm, unsigned long type, u32 v);

int kvm_riscv_aia_aplic_get_attr(struct kvm *kvm, unsigned long type, u32 *v);

int kvm_riscv_aia_aplic_has_attr(struct kvm *kvm, unsigned long type);

int kvm_riscv_aia_aplic_inject(struct kvm *kvm, u32 source, bool level);

int kvm_riscv_aia_aplic_init(struct kvm *kvm);

void kvm_riscv_aia_aplic_cleanup(struct kvm *kvm);



#ifdef CONFIG_32BIT

void kvm_riscv_vcpu_aia_flush_interrupts(struct kvm_vcpu *vcpu);
@@ -93,31 +148,23 @@ int kvm_riscv_vcpu_aia_rmw_ireg(struct kvm_vcpu *vcpu, unsigned int csr_num, 
{ .base = CSR_SIREG,      .count = 1, .func = kvm_riscv_vcpu_aia_rmw_ireg }, \

{ .base = CSR_STOPEI,     .count = 1, .func = kvm_riscv_vcpu_aia_rmw_topei },



static inline int kvm_riscv_vcpu_aia_update(struct kvm_vcpu *vcpu)

{

	return 1;

}

int kvm_riscv_vcpu_aia_update(struct kvm_vcpu *vcpu);

void kvm_riscv_vcpu_aia_reset(struct kvm_vcpu *vcpu);

int kvm_riscv_vcpu_aia_init(struct kvm_vcpu *vcpu);

void kvm_riscv_vcpu_aia_deinit(struct kvm_vcpu *vcpu);



static inline void kvm_riscv_vcpu_aia_reset(struct kvm_vcpu *vcpu)

{

}

int kvm_riscv_aia_inject_msi_by_id(struct kvm *kvm, u32 hart_index,

				   u32 guest_index, u32 iid);

int kvm_riscv_aia_inject_msi(struct kvm *kvm, struct kvm_msi *msi);

int kvm_riscv_aia_inject_irq(struct kvm *kvm, unsigned int irq, bool level);



static inline int kvm_riscv_vcpu_aia_init(struct kvm_vcpu *vcpu)

{

	return 0;

}

void kvm_riscv_aia_init_vm(struct kvm *kvm);

void kvm_riscv_aia_destroy_vm(struct kvm *kvm);



static inline void kvm_riscv_vcpu_aia_deinit(struct kvm_vcpu *vcpu)

{

}



static inline void kvm_riscv_aia_init_vm(struct kvm *kvm)

{

}



static inline void kvm_riscv_aia_destroy_vm(struct kvm *kvm)

{

}

int kvm_riscv_aia_alloc_hgei(int cpu, struct kvm_vcpu *owner,

			     void __iomem **hgei_va, phys_addr_t *hgei_pa);

void kvm_riscv_aia_free_hgei(int cpu, int hgei);

void kvm_riscv_aia_wakeon_hgei(struct kvm_vcpu *owner, bool enable);



void kvm_riscv_aia_enable(void);

void kvm_riscv_aia_disable(void);

arch/riscv/include/asm/kvm_aia_aplic.h

0 → 100644
+58 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (C) 2021 Western Digital Corporation or its affiliates.

 * Copyright (C) 2022 Ventana Micro Systems Inc.

 */

#ifndef __KVM_RISCV_AIA_IMSIC_H

#define __KVM_RISCV_AIA_IMSIC_H



#include <linux/bitops.h>



#define APLIC_MAX_IDC			BIT(14)

#define APLIC_MAX_SOURCE		1024



#define APLIC_DOMAINCFG			0x0000

#define APLIC_DOMAINCFG_RDONLY		0x80000000

#define APLIC_DOMAINCFG_IE		BIT(8)

#define APLIC_DOMAINCFG_DM		BIT(2)

#define APLIC_DOMAINCFG_BE		BIT(0)



#define APLIC_SOURCECFG_BASE		0x0004

#define APLIC_SOURCECFG_D		BIT(10)

#define APLIC_SOURCECFG_CHILDIDX_MASK	0x000003ff

#define APLIC_SOURCECFG_SM_MASK	0x00000007

#define APLIC_SOURCECFG_SM_INACTIVE	0x0

#define APLIC_SOURCECFG_SM_DETACH	0x1

#define APLIC_SOURCECFG_SM_EDGE_RISE	0x4

#define APLIC_SOURCECFG_SM_EDGE_FALL	0x5

#define APLIC_SOURCECFG_SM_LEVEL_HIGH	0x6

#define APLIC_SOURCECFG_SM_LEVEL_LOW	0x7



#define APLIC_IRQBITS_PER_REG		32



#define APLIC_SETIP_BASE		0x1c00

#define APLIC_SETIPNUM			0x1cdc



#define APLIC_CLRIP_BASE		0x1d00

#define APLIC_CLRIPNUM			0x1ddc



#define APLIC_SETIE_BASE		0x1e00

#define APLIC_SETIENUM			0x1edc



#define APLIC_CLRIE_BASE		0x1f00

#define APLIC_CLRIENUM			0x1fdc



#define APLIC_SETIPNUM_LE		0x2000

#define APLIC_SETIPNUM_BE		0x2004



#define APLIC_GENMSI			0x3000



#define APLIC_TARGET_BASE		0x3004

#define APLIC_TARGET_HART_IDX_SHIFT	18

#define APLIC_TARGET_HART_IDX_MASK	0x3fff

#define APLIC_TARGET_GUEST_IDX_SHIFT	12

#define APLIC_TARGET_GUEST_IDX_MASK	0x3f

#define APLIC_TARGET_IPRIO_MASK	0xff

#define APLIC_TARGET_EIID_MASK	0x7ff



#endif

arch/riscv/include/asm/kvm_aia_imsic.h

0 → 100644
+38 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (C) 2021 Western Digital Corporation or its affiliates.

 * Copyright (C) 2022 Ventana Micro Systems Inc.

 */

#ifndef __KVM_RISCV_AIA_IMSIC_H

#define __KVM_RISCV_AIA_IMSIC_H



#include <linux/types.h>

#include <asm/csr.h>



#define IMSIC_MMIO_PAGE_SHIFT		12

#define IMSIC_MMIO_PAGE_SZ		(1UL << IMSIC_MMIO_PAGE_SHIFT)

#define IMSIC_MMIO_PAGE_LE		0x00

#define IMSIC_MMIO_PAGE_BE		0x04



#define IMSIC_MIN_ID			63

#define IMSIC_MAX_ID			2048



#define IMSIC_EIDELIVERY		0x70



#define IMSIC_EITHRESHOLD		0x72



#define IMSIC_EIP0			0x80

#define IMSIC_EIP63			0xbf

#define IMSIC_EIPx_BITS			32



#define IMSIC_EIE0			0xc0

#define IMSIC_EIE63			0xff

#define IMSIC_EIEx_BITS			32



#define IMSIC_FIRST			IMSIC_EIDELIVERY

#define IMSIC_LAST			IMSIC_EIE63



#define IMSIC_MMIO_SETIPNUM_LE		0x00

#define IMSIC_MMIO_SETIPNUM_BE		0x04



#endif

arch/riscv/include/asm/kvm_host.h

+4 −0
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ 


#define KVM_VCPU_MAX_FEATURES		0



#define KVM_IRQCHIP_NUM_PINS		1024



#define KVM_REQ_SLEEP \

	KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)

#define KVM_REQ_VCPU_RESET		KVM_ARCH_REQ(1)
@@ -318,6 +320,8 @@ int kvm_riscv_gstage_vmid_init(struct kvm *kvm); 
bool kvm_riscv_gstage_vmid_ver_changed(struct kvm_vmid *vmid);

void kvm_riscv_gstage_vmid_update(struct kvm_vcpu *vcpu);



int kvm_riscv_setup_default_irq_routing(struct kvm *kvm, u32 lines);



void __kvm_riscv_unpriv_trap(void);



unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vcpu *vcpu,