Commit b51f86e9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf_urgent_for_v5.18_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf fixes from Borislav Petkov:

 - A couple of fixes to cgroup-related handling of perf events

 - A couple of fixes to event encoding on Sapphire Rapids

 - Pass event caps of inherited events so that perf doesn't fail wrongly
   at fork()

 - Add support for a new Raptor Lake CPU

* tag 'perf_urgent_for_v5.18_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/core: Always set cpuctx cgrp when enable cgroup event
  perf/core: Fix perf_cgroup_switch()
  perf/core: Use perf_cgroup_info->active to check if cgroup is active
  perf/core: Don't pass task around when ctx sched in
  perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids
  perf/x86/intel: Don't extend the pseudo-encoding to GP counters
  perf/core: Inherit event_caps
  perf/x86/uncore: Add Raptor Lake uncore support
  perf/x86/msr: Add Raptor Lake CPU support
  perf/x86/cstate: Add Raptor Lake support
  perf/x86: Add Intel Raptor Lake support
parents 50c94de6 e19cd0b6

arch/x86/events/intel/core.c

+7 −2
Original line number Diff line number Diff line
@@ -302,7 +302,7 @@ static struct extra_reg intel_spr_extra_regs[] __read_mostly = { 
	INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),

	INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),

	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),

	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),

	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),

	INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),

	INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),

	EVENT_EXTRA_END
@@ -5536,7 +5536,11 @@ static void intel_pmu_check_event_constraints(struct event_constraint *event_con 
			/* Disabled fixed counters which are not in CPUID */

			c->idxmsk64 &= intel_ctrl;



			if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES)

			/*

			 * Don't extend the pseudo-encoding to the

			 * generic counters

			 */

			if (!use_fixed_pseudo_encoding(c->code))

				c->idxmsk64 |= (1ULL << num_counters) - 1;

		}

		c->idxmsk64 &=
@@ -6212,6 +6216,7 @@ __init int intel_pmu_init(void) 


	case INTEL_FAM6_ALDERLAKE:

	case INTEL_FAM6_ALDERLAKE_L:

	case INTEL_FAM6_RAPTORLAKE:

		/*

		 * Alder Lake has 2 types of CPU, core and atom.

		 *

arch/x86/events/intel/cstate.c

+12 −10
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ 
 * Model specific counters:

 *	MSR_CORE_C1_RES: CORE C1 Residency Counter

 *			 perf code: 0x00

 *			 Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL

 *			 Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL

 *			 Scope: Core (each processor core has a MSR)

 *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter

 *			       perf code: 0x01
@@ -51,49 +51,50 @@ 
 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,

 *						TGL,TNT,RKL,ADL

 *						TGL,TNT,RKL,ADL,RPL

 *			       Scope: Core

 *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter

 *			       perf code: 0x03

 *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,

 *						ICL,TGL,RKL,ADL

 *						ICL,TGL,RKL,ADL,RPL

 *			       Scope: Core

 *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.

 *			       perf code: 0x00

 *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,

 *						KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL

 *						KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,

 *						RPL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.

 *			       perf code: 0x01

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,

 *						GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,

 *						ADL

 *						ADL,RPL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.

 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,

 *						TGL,TNT,RKL,ADL

 *						TGL,TNT,RKL,ADL,RPL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.

 *			       perf code: 0x03

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,

 *						KBL,CML,ICL,TGL,RKL,ADL

 *						KBL,CML,ICL,TGL,RKL,ADL,RPL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C8_RESIDENCY:  Package C8 Residency Counter.

 *			       perf code: 0x04

 *			       Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,

 *						ADL

 *						ADL,RPL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C9_RESIDENCY:  Package C9 Residency Counter.

 *			       perf code: 0x05

 *			       Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,

 *						ADL

 *						ADL,RPL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.

 *			       perf code: 0x06

 *			       Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,

 *						TNT,RKL,ADL

 *						TNT,RKL,ADL,RPL

 *			       Scope: Package (physical package)

 *

 */
@@ -680,6 +681,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,		&icl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&adl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&adl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,		&adl_cstates),

	{ },

};

MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);

arch/x86/events/intel/uncore.c

+1 −0
Original line number Diff line number Diff line
@@ -1828,6 +1828,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,		&rkl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,		&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&spr_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	&snr_uncore_init),

	{},

arch/x86/events/intel/uncore_snb.c

+20 −0
Original line number Diff line number Diff line
@@ -79,6 +79,10 @@ 
#define PCI_DEVICE_ID_INTEL_ADL_14_IMC		0x4650

#define PCI_DEVICE_ID_INTEL_ADL_15_IMC		0x4668

#define PCI_DEVICE_ID_INTEL_ADL_16_IMC		0x4670

#define PCI_DEVICE_ID_INTEL_RPL_1_IMC		0xA700

#define PCI_DEVICE_ID_INTEL_RPL_2_IMC		0xA702

#define PCI_DEVICE_ID_INTEL_RPL_3_IMC		0xA706

#define PCI_DEVICE_ID_INTEL_RPL_4_IMC		0xA709



/* SNB event control */

#define SNB_UNC_CTL_EV_SEL_MASK			0x000000ff
@@ -1406,6 +1410,22 @@ static const struct pci_device_id tgl_uncore_pci_ids[] = { 
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_16_IMC),

		.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),

	},

	{ /* IMC */

		PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_1_IMC),

		.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),

	},

	{ /* IMC */

		PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_2_IMC),

		.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),

	},

	{ /* IMC */

		PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_3_IMC),

		.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),

	},

	{ /* IMC */

		PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_4_IMC),

		.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),

	},

	{ /* end: all zeroes */ }

};

arch/x86/events/msr.c

+1 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ static bool test_intel(int idx, void *data) 
	case INTEL_FAM6_ROCKETLAKE:

	case INTEL_FAM6_ALDERLAKE:

	case INTEL_FAM6_ALDERLAKE_L:

	case INTEL_FAM6_RAPTORLAKE:

		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)

			return true;

		break;