Commit b4e9b876 authored by Angela Czubak's avatar Angela Czubak Committed by Jakub Kicinski
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octeontx2-af: Fix LMAC config in cgx_lmac_rx_tx_enable



PF netdev can request AF to enable or disable reception and transmission
on assigned CGX::LMAC. The current code instead of disabling or enabling
'reception and transmission' also disables/enable the LMAC. This patch
fixes this issue.

Fixes: 1435f66a ("octeontx2-af: CGX Rx/Tx enable/disable mbox handlers")
Signed-off-by: default avatarAngela Czubak <aczubak@marvell.com>
Signed-off-by: default avatarHariprasad Kelam <hkelam@marvell.com>
Reviewed-by: default avatarLeon Romanovsky <leonro@nvidia.com>
Link: https://lore.kernel.org/r/20230105160107.17638-1-hkelam@marvell.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent c244c092
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+2 −2
Original line number Diff line number Diff line
@@ -774,9 +774,9 @@ int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable)

	cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
	if (enable)
		cfg |= CMR_EN | DATA_PKT_RX_EN | DATA_PKT_TX_EN;
		cfg |= DATA_PKT_RX_EN | DATA_PKT_TX_EN;
	else
		cfg &= ~(CMR_EN | DATA_PKT_RX_EN | DATA_PKT_TX_EN);
		cfg &= ~(DATA_PKT_RX_EN | DATA_PKT_TX_EN);
	cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
	return 0;
}
+0 −1
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@
#define CMR_P2X_SEL_SHIFT		59ULL
#define CMR_P2X_SEL_NIX0		1ULL
#define CMR_P2X_SEL_NIX1		2ULL
#define CMR_EN				BIT_ULL(55)
#define DATA_PKT_TX_EN			BIT_ULL(53)
#define DATA_PKT_RX_EN			BIT_ULL(54)
#define CGX_LMAC_TYPE_SHIFT		40