Commit b4db1d22 authored by Jie Wang's avatar Jie Wang Committed by Aichun Shi
Browse files

crypto: qat - add support for 420xx devices 

mainline inclusion
from mainline-v6.8-rc1
commit fcf60f4bcf54952cc14d14178c358be222dbeb43
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I9A5BW
CVE: N/A
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=fcf60f4bcf54952cc14d14178c358be222dbeb43



-------------------------------------

Add support for 420xx devices by including a new device driver that
supports such devices, updates to the firmware loader and capabilities.

Compared to 4xxx devices, 420xx devices have more acceleration engines
(16 service engines and 1 admin) and support the wireless cipher
algorithms ZUC and Snow 3G.

Intel-SIG: commit fcf60f4bcf54 crypto: qat - add support for 420xx devices
Backport to support QAT in-tree driver

Signed-off-by: default avatarJie Wang <jie.wang@intel.com>
Co-developed-by: default avatarDong Xie <dong.xie@intel.com>
Signed-off-by: default avatarDong Xie <dong.xie@intel.com>
Reviewed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
[ Aichun Shi: amend commit log ]
Signed-off-by: default avatarAichun Shi <aichun.shi@intel.com>
parent c5af0cd0

drivers/crypto/intel/qat/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -59,6 +59,17 @@ config CRYPTO_DEV_QAT_4XXX 
	  To compile this as a module, choose M here: the module

	  will be called qat_4xxx.



config CRYPTO_DEV_QAT_420XX

	tristate "Support for Intel(R) QAT_420XX"

	depends on PCI && (!CPU_BIG_ENDIAN || COMPILE_TEST)

	select CRYPTO_DEV_QAT

	help

	  Support for Intel(R) QuickAssist Technology QAT_420xx

	  for accelerating crypto and compression workloads.



	  To compile this as a module, choose M here: the module

	  will be called qat_420xx.



config CRYPTO_DEV_QAT_DH895xCCVF

	tristate "Support for Intel(R) DH895xCC Virtual Function"

	depends on PCI && (!CPU_BIG_ENDIAN || COMPILE_TEST)

drivers/crypto/intel/qat/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ obj-$(CONFIG_CRYPTO_DEV_QAT_DH895xCC) += qat_dh895xcc/ 
obj-$(CONFIG_CRYPTO_DEV_QAT_C3XXX) += qat_c3xxx/

obj-$(CONFIG_CRYPTO_DEV_QAT_C62X) += qat_c62x/

obj-$(CONFIG_CRYPTO_DEV_QAT_4XXX) += qat_4xxx/

obj-$(CONFIG_CRYPTO_DEV_QAT_420XX) += qat_420xx/

obj-$(CONFIG_CRYPTO_DEV_QAT_DH895xCCVF) += qat_dh895xccvf/

obj-$(CONFIG_CRYPTO_DEV_QAT_C3XXXVF) += qat_c3xxxvf/

obj-$(CONFIG_CRYPTO_DEV_QAT_C62XVF) += qat_c62xvf/

drivers/crypto/intel/qat/qat_420xx/Makefile

0 → 100644
+4 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

ccflags-y := -I $(srctree)/$(src)/../qat_common

obj-$(CONFIG_CRYPTO_DEV_QAT_420XX) += qat_420xx.o

qat_420xx-objs := adf_drv.o adf_420xx_hw_data.o

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

0 → 100644
+552 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright(c) 2023 Intel Corporation */

#include <linux/iopoll.h>

#include <adf_accel_devices.h>

#include <adf_admin.h>

#include <adf_cfg.h>

#include <adf_cfg_services.h>

#include <adf_clock.h>

#include <adf_common_drv.h>

#include <adf_fw_config.h>

#include <adf_gen4_config.h>

#include <adf_gen4_dc.h>

#include <adf_gen4_hw_data.h>

#include <adf_gen4_pfvf.h>

#include <adf_gen4_pm.h>

#include <adf_gen4_ras.h>

#include <adf_gen4_timer.h>

#include "adf_420xx_hw_data.h"

#include "icp_qat_hw.h"



#define ADF_AE_GROUP_0		GENMASK(3, 0)

#define ADF_AE_GROUP_1		GENMASK(7, 4)

#define ADF_AE_GROUP_2		GENMASK(11, 8)

#define ADF_AE_GROUP_3		GENMASK(15, 12)

#define ADF_AE_GROUP_4		BIT(16)



static const char * const adf_420xx_fw_objs[] = {

	[ADF_FW_SYM_OBJ] =  ADF_420XX_SYM_OBJ,

	[ADF_FW_ASYM_OBJ] =  ADF_420XX_ASYM_OBJ,

	[ADF_FW_DC_OBJ] =  ADF_420XX_DC_OBJ,

	[ADF_FW_ADMIN_OBJ] = ADF_420XX_ADMIN_OBJ,

};



static const struct adf_fw_config adf_fw_cy_config[] = {

	{ADF_AE_GROUP_3, ADF_FW_SYM_OBJ},

	{ADF_AE_GROUP_2, ADF_FW_ASYM_OBJ},

	{ADF_AE_GROUP_1, ADF_FW_SYM_OBJ},

	{ADF_AE_GROUP_0, ADF_FW_ASYM_OBJ},

	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},

};



static const struct adf_fw_config adf_fw_dc_config[] = {

	{ADF_AE_GROUP_1, ADF_FW_DC_OBJ},

	{ADF_AE_GROUP_0, ADF_FW_DC_OBJ},

	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},

};



static const struct adf_fw_config adf_fw_sym_config[] = {

	{ADF_AE_GROUP_3, ADF_FW_SYM_OBJ},

	{ADF_AE_GROUP_2, ADF_FW_SYM_OBJ},

	{ADF_AE_GROUP_1, ADF_FW_SYM_OBJ},

	{ADF_AE_GROUP_0, ADF_FW_SYM_OBJ},

	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},

};



static const struct adf_fw_config adf_fw_asym_config[] = {

	{ADF_AE_GROUP_3, ADF_FW_ASYM_OBJ},

	{ADF_AE_GROUP_2, ADF_FW_ASYM_OBJ},

	{ADF_AE_GROUP_1, ADF_FW_ASYM_OBJ},

	{ADF_AE_GROUP_0, ADF_FW_ASYM_OBJ},

	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},

};



static const struct adf_fw_config adf_fw_asym_dc_config[] = {

	{ADF_AE_GROUP_3, ADF_FW_ASYM_OBJ},

	{ADF_AE_GROUP_2, ADF_FW_ASYM_OBJ},

	{ADF_AE_GROUP_1, ADF_FW_ASYM_OBJ},

	{ADF_AE_GROUP_0, ADF_FW_DC_OBJ},

	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},

};



static const struct adf_fw_config adf_fw_sym_dc_config[] = {

	{ADF_AE_GROUP_2, ADF_FW_SYM_OBJ},

	{ADF_AE_GROUP_1, ADF_FW_SYM_OBJ},

	{ADF_AE_GROUP_0, ADF_FW_DC_OBJ},

	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},

};



static const struct adf_fw_config adf_fw_dcc_config[] = {

	{ADF_AE_GROUP_1, ADF_FW_DC_OBJ},

	{ADF_AE_GROUP_0, ADF_FW_SYM_OBJ},

	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},

};



/* Worker thread to service arbiter mappings */

static const u32 default_thrd_to_arb_map[ADF_420XX_MAX_ACCELENGINES] = {

	0x00000055, 0x00000055, 0x00000055, 0x00000055,

	0x0000AAAA, 0x0000AAAA, 0x0000AAAA, 0x0000AAAA,

	0x00000055, 0x00000055, 0x00000055, 0x00000055,

	0x0000AAAA, 0x0000AAAA, 0x0000AAAA, 0x0000AAAA,

	0x0

};



static const u32 thrd_to_arb_map_asym[ADF_420XX_MAX_ACCELENGINES] = {

	0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,

	0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,

	0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,

	0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,

	0x0

};



static const u32 thrd_to_arb_map_sym[ADF_420XX_MAX_ACCELENGINES] = {

	0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,

	0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,

	0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,

	0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,

	0x0

};



static const u32 thrd_to_arb_map_asym_dc[ADF_420XX_MAX_ACCELENGINES] = {

	0x00000055, 0x00000055, 0x00000055, 0x00000055,

	0x000000AA, 0x000000AA, 0x000000AA, 0x000000AA,

	0x000000AA, 0x000000AA, 0x000000AA, 0x000000AA,

	0x000000AA, 0x000000AA, 0x000000AA, 0x000000AA,

	0x0

};



static const u32 thrd_to_arb_map_sym_dc[ADF_420XX_MAX_ACCELENGINES] = {

	0x00000055, 0x00000055, 0x00000055, 0x00000055,

	0x0000AAAA, 0x0000AAAA, 0x0000AAAA, 0x0000AAAA,

	0x0000AAAA, 0x0000AAAA, 0x0000AAAA, 0x0000AAAA,

	0x00000000, 0x00000000, 0x00000000, 0x00000000,

	0x0

};



static const u32 thrd_to_arb_map_dc[ADF_420XX_MAX_ACCELENGINES] = {

	0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,

	0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,

	0x00000000, 0x00000000, 0x00000000, 0x00000000,

	0x00000000, 0x00000000, 0x00000000, 0x00000000,

	0x0

};



static const u32 thrd_to_arb_map_dcc[ADF_420XX_MAX_ACCELENGINES] = {

	0x00000000, 0x00000000, 0x00000000, 0x00000000,

	0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,

	0x00000000, 0x00000000, 0x00000000, 0x00000000,

	0x00000000, 0x00000000, 0x00000000, 0x00000000,

	0x0

};



static struct adf_hw_device_class adf_420xx_class = {

	.name = ADF_420XX_DEVICE_NAME,

	.type = DEV_420XX,

	.instances = 0,

};



static u32 get_ae_mask(struct adf_hw_device_data *self)

{

	u32 me_disable = self->fuses;



	return ~me_disable & ADF_420XX_ACCELENGINES_MASK;

}



static u32 uof_get_num_objs(struct adf_accel_dev *accel_dev)

{

	switch (adf_get_service_enabled(accel_dev)) {

	case SVC_CY:

	case SVC_CY2:

		return ARRAY_SIZE(adf_fw_cy_config);

	case SVC_DC:

		return ARRAY_SIZE(adf_fw_dc_config);

	case SVC_DCC:

		return ARRAY_SIZE(adf_fw_dcc_config);

	case SVC_SYM:

		return ARRAY_SIZE(adf_fw_sym_config);

	case SVC_ASYM:

		return ARRAY_SIZE(adf_fw_asym_config);

	case SVC_ASYM_DC:

	case SVC_DC_ASYM:

		return ARRAY_SIZE(adf_fw_asym_dc_config);

	case SVC_SYM_DC:

	case SVC_DC_SYM:

		return ARRAY_SIZE(adf_fw_sym_dc_config);

	default:

		return 0;

	}

}



static const struct adf_fw_config *get_fw_config(struct adf_accel_dev *accel_dev)

{

	switch (adf_get_service_enabled(accel_dev)) {

	case SVC_CY:

	case SVC_CY2:

		return adf_fw_cy_config;

	case SVC_DC:

		return adf_fw_dc_config;

	case SVC_DCC:

		return adf_fw_dcc_config;

	case SVC_SYM:

		return adf_fw_sym_config;

	case SVC_ASYM:

		return adf_fw_asym_config;

	case SVC_ASYM_DC:

	case SVC_DC_ASYM:

		return adf_fw_asym_dc_config;

	case SVC_SYM_DC:

	case SVC_DC_SYM:

		return adf_fw_sym_dc_config;

	default:

		return NULL;

	}

}



static void update_ae_mask(struct adf_accel_dev *accel_dev)

{

	struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

	const struct adf_fw_config *fw_config;

	u32 config_ae_mask = 0;

	u32 ae_mask, num_objs;

	int i;



	ae_mask = get_ae_mask(hw_data);



	/* Modify the AE mask based on the firmware configuration loaded */

	fw_config = get_fw_config(accel_dev);

	num_objs = uof_get_num_objs(accel_dev);



	config_ae_mask |= ADF_420XX_ADMIN_AE_MASK;

	for (i = 0; i < num_objs; i++)

		config_ae_mask |= fw_config[i].ae_mask;



	hw_data->ae_mask = ae_mask & config_ae_mask;

}



static u32 get_accel_cap(struct adf_accel_dev *accel_dev)

{

	u32 capabilities_sym, capabilities_asym, capabilities_dc;

	struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;

	u32 capabilities_dcc;

	u32 fusectl1;



	/* As a side effect, update ae_mask based on configuration */

	update_ae_mask(accel_dev);



	/* Read accelerator capabilities mask */

	pci_read_config_dword(pdev, ADF_GEN4_FUSECTL1_OFFSET, &fusectl1);



	capabilities_sym = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |

			  ICP_ACCEL_CAPABILITIES_CIPHER |

			  ICP_ACCEL_CAPABILITIES_AUTHENTICATION |

			  ICP_ACCEL_CAPABILITIES_SHA3 |

			  ICP_ACCEL_CAPABILITIES_SHA3_EXT |

			  ICP_ACCEL_CAPABILITIES_HKDF |

			  ICP_ACCEL_CAPABILITIES_CHACHA_POLY |

			  ICP_ACCEL_CAPABILITIES_AESGCM_SPC |

			  ICP_ACCEL_CAPABILITIES_SM3 |

			  ICP_ACCEL_CAPABILITIES_SM4 |

			  ICP_ACCEL_CAPABILITIES_AES_V2 |

			  ICP_ACCEL_CAPABILITIES_ZUC |

			  ICP_ACCEL_CAPABILITIES_ZUC_256 |

			  ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT |

			  ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN;



	/* A set bit in fusectl1 means the feature is OFF in this SKU */

	if (fusectl1 & ICP_ACCEL_GEN4_MASK_CIPHER_SLICE) {

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_HKDF;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;

	}



	if (fusectl1 & ICP_ACCEL_GEN4_MASK_UCS_SLICE) {

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_AES_V2;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;

	}



	if (fusectl1 & ICP_ACCEL_GEN4_MASK_AUTH_SLICE) {

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SHA3;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;

	}



	if (fusectl1 & ICP_ACCEL_GEN4_MASK_SMX_SLICE) {

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SM3;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SM4;

	}



	if (fusectl1 & ICP_ACCEL_GEN4_MASK_WCP_WAT_SLICE) {

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC_256;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT;

	}



	if (fusectl1 & ICP_ACCEL_GEN4_MASK_EIA3_SLICE) {

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC_256;

	}



	if (fusectl1 & ICP_ACCEL_GEN4_MASK_ZUC_256_SLICE)

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC_256;



	capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |

			  ICP_ACCEL_CAPABILITIES_SM2 |

			  ICP_ACCEL_CAPABILITIES_ECEDMONT;



	if (fusectl1 & ICP_ACCEL_GEN4_MASK_PKE_SLICE) {

		capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;

		capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_SM2;

		capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;

	}



	capabilities_dc = ICP_ACCEL_CAPABILITIES_COMPRESSION |

			  ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION |

			  ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION |

			  ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;



	if (fusectl1 & ICP_ACCEL_GEN4_MASK_COMPRESS_SLICE) {

		capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;

		capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION;

		capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;

		capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;

	}



	switch (adf_get_service_enabled(accel_dev)) {

	case SVC_CY:

	case SVC_CY2:

		return capabilities_sym | capabilities_asym;

	case SVC_DC:

		return capabilities_dc;

	case SVC_DCC:

		/*

		 * Sym capabilities are available for chaining operations,

		 * but sym crypto instances cannot be supported

		 */

		capabilities_dcc = capabilities_dc | capabilities_sym;

		capabilities_dcc &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;

		return capabilities_dcc;

	case SVC_SYM:

		return capabilities_sym;

	case SVC_ASYM:

		return capabilities_asym;

	case SVC_ASYM_DC:

	case SVC_DC_ASYM:

		return capabilities_asym | capabilities_dc;

	case SVC_SYM_DC:

	case SVC_DC_SYM:

		return capabilities_sym | capabilities_dc;

	default:

		return 0;

	}

}



static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)

{

	switch (adf_get_service_enabled(accel_dev)) {

	case SVC_ASYM:

		return thrd_to_arb_map_asym;

	case SVC_SYM:

		return thrd_to_arb_map_sym;

	case SVC_DC:

		return thrd_to_arb_map_dc;

	case SVC_DCC:

		return thrd_to_arb_map_dcc;

	case SVC_ASYM_DC:

	case SVC_DC_ASYM:

		return thrd_to_arb_map_asym_dc;

	case SVC_DC_SYM:

	case SVC_SYM_DC:

		return thrd_to_arb_map_sym_dc;

	default:

		return default_thrd_to_arb_map;

	}

}



static void adf_init_rl_data(struct adf_rl_hw_data *rl_data)

{

	rl_data->pciout_tb_offset = ADF_GEN4_RL_TOKEN_PCIEOUT_BUCKET_OFFSET;

	rl_data->pciin_tb_offset = ADF_GEN4_RL_TOKEN_PCIEIN_BUCKET_OFFSET;

	rl_data->r2l_offset = ADF_GEN4_RL_R2L_OFFSET;

	rl_data->l2c_offset = ADF_GEN4_RL_L2C_OFFSET;

	rl_data->c2s_offset = ADF_GEN4_RL_C2S_OFFSET;



	rl_data->pcie_scale_div = ADF_420XX_RL_PCIE_SCALE_FACTOR_DIV;

	rl_data->pcie_scale_mul = ADF_420XX_RL_PCIE_SCALE_FACTOR_MUL;

	rl_data->dcpr_correction = ADF_420XX_RL_DCPR_CORRECTION;

	rl_data->max_tp[ADF_SVC_ASYM] = ADF_420XX_RL_MAX_TP_ASYM;

	rl_data->max_tp[ADF_SVC_SYM] = ADF_420XX_RL_MAX_TP_SYM;

	rl_data->max_tp[ADF_SVC_DC] = ADF_420XX_RL_MAX_TP_DC;

	rl_data->scan_interval = ADF_420XX_RL_SCANS_PER_SEC;

	rl_data->scale_ref = ADF_420XX_RL_SLICE_REF;

}



enum adf_rp_groups {

	RP_GROUP_0 = 0,

	RP_GROUP_1,

	RP_GROUP_COUNT

};



static u16 get_ring_to_svc_map(struct adf_accel_dev *accel_dev)

{

	enum adf_cfg_service_type rps[RP_GROUP_COUNT] = { };

	const struct adf_fw_config *fw_config;

	u16 ring_to_svc_map;

	int i, j;



	fw_config = get_fw_config(accel_dev);

	if (!fw_config)

		return 0;



	for (i = 0; i < RP_GROUP_COUNT; i++) {

		switch (fw_config[i].ae_mask) {

		case ADF_AE_GROUP_0:

			j = RP_GROUP_0;

			break;

		case ADF_AE_GROUP_1:

			j = RP_GROUP_1;

			break;

		default:

			return 0;

		}



		switch (fw_config[i].obj) {

		case ADF_FW_SYM_OBJ:

			rps[j] = SYM;

			break;

		case ADF_FW_ASYM_OBJ:

			rps[j] = ASYM;

			break;

		case ADF_FW_DC_OBJ:

			rps[j] = COMP;

			break;

		default:

			rps[j] = 0;

			break;

		}

	}



	ring_to_svc_map = rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_0_SHIFT |

			  rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_1_SHIFT |

			  rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_2_SHIFT |

			  rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_3_SHIFT;



	return ring_to_svc_map;

}



static const char *uof_get_name(struct adf_accel_dev *accel_dev, u32 obj_num,

				const char * const fw_objs[], int num_objs)

{

	const struct adf_fw_config *fw_config;

	int id;



	fw_config = get_fw_config(accel_dev);

	if (fw_config)

		id = fw_config[obj_num].obj;

	else

		id = -EINVAL;



	if (id < 0 || id > num_objs)

		return NULL;



	return fw_objs[id];

}



static const char *uof_get_name_420xx(struct adf_accel_dev *accel_dev, u32 obj_num)

{

	int num_fw_objs = ARRAY_SIZE(adf_420xx_fw_objs);



	return uof_get_name(accel_dev, obj_num, adf_420xx_fw_objs, num_fw_objs);

}



static u32 uof_get_ae_mask(struct adf_accel_dev *accel_dev, u32 obj_num)

{

	const struct adf_fw_config *fw_config;



	fw_config = get_fw_config(accel_dev);

	if (!fw_config)

		return 0;



	return fw_config[obj_num].ae_mask;

}



static void adf_gen4_set_err_mask(struct adf_dev_err_mask *dev_err_mask)

{

	dev_err_mask->cppagentcmdpar_mask = ADF_420XX_HICPPAGENTCMDPARERRLOG_MASK;

	dev_err_mask->parerr_ath_cph_mask = ADF_420XX_PARITYERRORMASK_ATH_CPH_MASK;

	dev_err_mask->parerr_cpr_xlt_mask = ADF_420XX_PARITYERRORMASK_CPR_XLT_MASK;

	dev_err_mask->parerr_dcpr_ucs_mask = ADF_420XX_PARITYERRORMASK_DCPR_UCS_MASK;

	dev_err_mask->parerr_pke_mask = ADF_420XX_PARITYERRORMASK_PKE_MASK;

	dev_err_mask->ssmfeatren_mask = ADF_420XX_SSMFEATREN_MASK;

}



void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id)

{

	hw_data->dev_class = &adf_420xx_class;

	hw_data->instance_id = adf_420xx_class.instances++;

	hw_data->num_banks = ADF_GEN4_ETR_MAX_BANKS;

	hw_data->num_banks_per_vf = ADF_GEN4_NUM_BANKS_PER_VF;

	hw_data->num_rings_per_bank = ADF_GEN4_NUM_RINGS_PER_BANK;

	hw_data->num_accel = ADF_GEN4_MAX_ACCELERATORS;

	hw_data->num_engines = ADF_420XX_MAX_ACCELENGINES;

	hw_data->num_logical_accel = 1;

	hw_data->tx_rx_gap = ADF_GEN4_RX_RINGS_OFFSET;

	hw_data->tx_rings_mask = ADF_GEN4_TX_RINGS_MASK;

	hw_data->ring_to_svc_map = ADF_GEN4_DEFAULT_RING_TO_SRV_MAP;

	hw_data->alloc_irq = adf_isr_resource_alloc;

	hw_data->free_irq = adf_isr_resource_free;

	hw_data->enable_error_correction = adf_gen4_enable_error_correction;

	hw_data->get_accel_mask = adf_gen4_get_accel_mask;

	hw_data->get_ae_mask = get_ae_mask;

	hw_data->get_num_accels = adf_gen4_get_num_accels;

	hw_data->get_num_aes = adf_gen4_get_num_aes;

	hw_data->get_sram_bar_id = adf_gen4_get_sram_bar_id;

	hw_data->get_etr_bar_id = adf_gen4_get_etr_bar_id;

	hw_data->get_misc_bar_id = adf_gen4_get_misc_bar_id;

	hw_data->get_arb_info = adf_gen4_get_arb_info;

	hw_data->get_admin_info = adf_gen4_get_admin_info;

	hw_data->get_accel_cap = get_accel_cap;

	hw_data->get_sku = adf_gen4_get_sku;

	hw_data->init_admin_comms = adf_init_admin_comms;

	hw_data->exit_admin_comms = adf_exit_admin_comms;

	hw_data->send_admin_init = adf_send_admin_init;

	hw_data->init_arb = adf_init_arb;

	hw_data->exit_arb = adf_exit_arb;

	hw_data->get_arb_mapping = adf_get_arbiter_mapping;

	hw_data->enable_ints = adf_gen4_enable_ints;

	hw_data->init_device = adf_gen4_init_device;

	hw_data->reset_device = adf_reset_flr;

	hw_data->admin_ae_mask = ADF_420XX_ADMIN_AE_MASK;

	hw_data->fw_name = ADF_420XX_FW;

	hw_data->fw_mmp_name = ADF_420XX_MMP;

	hw_data->uof_get_name = uof_get_name_420xx;

	hw_data->uof_get_num_objs = uof_get_num_objs;

	hw_data->uof_get_ae_mask = uof_get_ae_mask;

	hw_data->set_msix_rttable = adf_gen4_set_msix_default_rttable;

	hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;

	hw_data->get_ring_to_svc_map = get_ring_to_svc_map;

	hw_data->disable_iov = adf_disable_sriov;

	hw_data->ring_pair_reset = adf_gen4_ring_pair_reset;

	hw_data->enable_pm = adf_gen4_enable_pm;

	hw_data->handle_pm_interrupt = adf_gen4_handle_pm_interrupt;

	hw_data->dev_config = adf_gen4_dev_config;

	hw_data->start_timer = adf_gen4_timer_start;

	hw_data->stop_timer = adf_gen4_timer_stop;

	hw_data->get_hb_clock = adf_gen4_get_heartbeat_clock;

	hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;

	hw_data->clock_frequency = ADF_420XX_AE_FREQ;



	adf_gen4_set_err_mask(&hw_data->dev_err_mask);

	adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);

	adf_gen4_init_pf_pfvf_ops(&hw_data->pfvf_ops);

	adf_gen4_init_dc_ops(&hw_data->dc_ops);

	adf_gen4_init_ras_ops(&hw_data->ras_ops);

	adf_init_rl_data(&hw_data->rl_data);

}



void adf_clean_hw_data_420xx(struct adf_hw_device_data *hw_data)

{

	hw_data->dev_class->instances--;

}

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright(c) 2023 Intel Corporation */

#ifndef ADF_420XX_HW_DATA_H_

#define ADF_420XX_HW_DATA_H_



#include <adf_accel_devices.h>



#define ADF_420XX_MAX_ACCELENGINES		17



#define ADF_420XX_ACCELENGINES_MASK		0x1FFFF

#define ADF_420XX_ADMIN_AE_MASK			0x10000



#define ADF_420XX_HICPPAGENTCMDPARERRLOG_MASK	(0xFF)

#define ADF_420XX_PARITYERRORMASK_ATH_CPH_MASK	(0xFF00FF)

#define ADF_420XX_PARITYERRORMASK_CPR_XLT_MASK	(0x10001)

#define ADF_420XX_PARITYERRORMASK_DCPR_UCS_MASK	(0xF0007)

#define ADF_420XX_PARITYERRORMASK_PKE_MASK	(0xFFF)

#define ADF_420XX_PARITYERRORMASK_WAT_WCP_MASK	(0x3FF03FF)



/*

 * SSMFEATREN bit mask

 * BIT(4) - enables parity detection on CPP

 * BIT(12) - enables the logging of push/pull data errors

 *	     in pperr register

 * BIT(16) - BIT(27) - enable parity detection on SPPs

 */

#define ADF_420XX_SSMFEATREN_MASK \

	(BIT(4) | BIT(12) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | \

	 BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27))



/* Firmware Binaries */

#define ADF_420XX_FW		"qat_420xx.bin"

#define ADF_420XX_MMP		"qat_420xx_mmp.bin"

#define ADF_420XX_SYM_OBJ	"qat_420xx_sym.bin"

#define ADF_420XX_DC_OBJ	"qat_420xx_dc.bin"

#define ADF_420XX_ASYM_OBJ	"qat_420xx_asym.bin"

#define ADF_420XX_ADMIN_OBJ	"qat_420xx_admin.bin"



/* RL constants */

#define ADF_420XX_RL_PCIE_SCALE_FACTOR_DIV	100

#define ADF_420XX_RL_PCIE_SCALE_FACTOR_MUL	102

#define ADF_420XX_RL_DCPR_CORRECTION		1

#define ADF_420XX_RL_SCANS_PER_SEC		954

#define ADF_420XX_RL_MAX_TP_ASYM		173750UL

#define ADF_420XX_RL_MAX_TP_SYM			95000UL

#define ADF_420XX_RL_MAX_TP_DC			40000UL

#define ADF_420XX_RL_SLICE_REF			1000UL



/* Clocks frequency */

#define ADF_420XX_AE_FREQ		(1000 * HZ_PER_MHZ)



void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id);

void adf_clean_hw_data_420xx(struct adf_hw_device_data *hw_data);



#endif