Commit b4d7049a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2021-07-08' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



drm/i915 changes for v5.15:

Features:
- Enable pipe DMC loading on XE-LPD and ADL-P (Anusha)
- Finally remove JSH and EHL force probe requirement (Tejas)

Refactoring and cleanups:
- Refactor and fix DDI buffer translations (Ville)
- Clean up FBC CFB allocation code (Ville, with a fix from Matthew)
- Finish INTEL_GEN() and friends macro conversions (Lucas)
- Misc display cleanups (Ville)

Fixes:
- PSR fixes and ADL-P workarounds (José)
- Fix drm infoframe state mismatch (Bhanuprakash)
- Force Type-C PHY disconnect during suspend/shutdown (Imre)
- Fix power sequence violation on some Chromebook models (Shawn)
- Fix VGA workaround to avoid screen flicker at boot (Emil)
- Fix display 12+ watermark workaround adjustment (Lucas)

Misc:
- Backmerge drm-next (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/878s2h6t5o.fsf@intel.com
parents 2734d6c1 cd5606aa

drivers/gpu/drm/i915/display/icl_dsi.c

+44 −2
Original line number Diff line number Diff line
@@ -729,8 +729,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);

	enum pipe pipe = intel_crtc->pipe;

	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);

	enum pipe pipe = crtc->pipe;

	u32 tmp;

	enum port port;

	enum transcoder dsi_trans;
@@ -1253,15 +1253,36 @@ static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 
	gen11_dsi_set_transcoder_timings(encoder, pipe_config);

}



/*

 * Wa_1409054076:icl,jsl,ehl

 * When pipe A is disabled and MIPI DSI is enabled on pipe B,

 * the AMT KVMR feature will incorrectly see pipe A as enabled.

 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave

 * it set while DSI is enabled on pipe B

 */

static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,

				     enum pipe pipe, bool enable)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B)

		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,

			     IGNORE_KVMR_PIPE_A,

			     enable ? IGNORE_KVMR_PIPE_A : 0);

}

static void gen11_dsi_enable(struct intel_atomic_state *state,

			     struct intel_encoder *encoder,

			     const struct intel_crtc_state *crtc_state,

			     const struct drm_connector_state *conn_state)

{

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);



	drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);



	/* Wa_1409054076:icl,jsl,ehl */

	icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);



	/* step6d: enable dsi transcoder */

	gen11_dsi_enable_transcoder(encoder);
@@ -1415,6 +1436,7 @@ static void gen11_dsi_disable(struct intel_atomic_state *state, 
			      const struct drm_connector_state *old_conn_state)

{

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc);



	/* step1: turn off backlight */

	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
@@ -1423,6 +1445,9 @@ static void gen11_dsi_disable(struct intel_atomic_state *state, 
	/* step2d,e: disable transcoder and wait */

	gen11_dsi_disable_transcoder(encoder);



	/* Wa_1409054076:icl,jsl,ehl */

	icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);



	/* step2f,g: powerdown panel */

	gen11_dsi_powerdown_panel(encoder);
@@ -1548,6 +1573,22 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, 
		pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;

}



static void gen11_dsi_sync_state(struct intel_encoder *encoder,

				 const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);

	enum pipe pipe = intel_crtc->pipe;



	/* wa verify 1409054076:icl,jsl,ehl */

	if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B &&

	    !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))

		drm_dbg_kms(&dev_priv->drm,

			    "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",

			    encoder->base.base.id,

			    encoder->base.name);

}



static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,

					struct intel_crtc_state *crtc_state)

{
@@ -1966,6 +2007,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) 
	encoder->post_disable = gen11_dsi_post_disable;

	encoder->port = port;

	encoder->get_config = gen11_dsi_get_config;

	encoder->sync_state = gen11_dsi_sync_state;

	encoder->update_pipe = intel_panel_update_backlight;

	encoder->compute_config = gen11_dsi_compute_config;

	encoder->get_hw_state = gen11_dsi_get_hw_state;

drivers/gpu/drm/i915/display/intel_crt.c

+3 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 
#include "intel_crt.h"

#include "intel_crtc.h"

#include "intel_ddi.h"

#include "intel_ddi_buf_trans.h"

#include "intel_de.h"

#include "intel_display_types.h"

#include "intel_fdi.h"
@@ -1081,6 +1082,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv) 
		crt->base.enable_clock = hsw_ddi_enable_clock;

		crt->base.disable_clock = hsw_ddi_disable_clock;

		crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;



		intel_ddi_buf_trans_init(&crt->base);

	} else {

		if (HAS_PCH_SPLIT(dev_priv)) {

			crt->base.compute_config = pch_crt_compute_config;

drivers/gpu/drm/i915/display/intel_crtc.c

+4 −4
Original line number Diff line number Diff line
@@ -163,12 +163,12 @@ static void intel_crtc_free(struct intel_crtc *crtc) 
	kfree(crtc);

}



static void intel_crtc_destroy(struct drm_crtc *crtc)

static void intel_crtc_destroy(struct drm_crtc *_crtc)

{

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_crtc *crtc = to_intel_crtc(_crtc);



	drm_crtc_cleanup(crtc);

	kfree(intel_crtc);

	drm_crtc_cleanup(&crtc->base);

	kfree(crtc);

}



static int intel_crtc_late_register(struct drm_crtc *crtc)

drivers/gpu/drm/i915/display/intel_ddi.c

+95 −115
Original line number Diff line number Diff line
@@ -95,24 +95,18 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 
 * values in advance. This function programs the correct values for

 * DP/eDP/FDI use cases.

 */

void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,

void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,

				const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u32 iboost_bit = 0;

	int i, n_entries;

	enum port port = encoder->port;

	const struct ddi_buf_trans *ddi_translations;



	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))

		ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,

							       &n_entries);

	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

		ddi_translations = intel_ddi_get_buf_trans_edp(encoder,

							       &n_entries);

	else

		ddi_translations = intel_ddi_get_buf_trans_dp(encoder,

							      &n_entries);

	const struct intel_ddi_buf_trans *ddi_translations;



	ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

		return;



	/* If we're boosting the current, set bit 31 of trans1 */

	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
@@ -121,9 +115,9 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 


	for (i = 0; i < n_entries; i++) {

		intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),

			       ddi_translations[i].trans1 | iboost_bit);

			       ddi_translations->entries[i].hsw.trans1 | iboost_bit);

		intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),

			       ddi_translations[i].trans2);

			       ddi_translations->entries[i].hsw.trans2);

	}

}
@@ -132,17 +126,17 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 
 * values in advance. This function programs the correct values for

 * HDMI/DVI use cases.

 */

static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,

static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,

					 const struct intel_crtc_state *crtc_state,

					 int level)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u32 iboost_bit = 0;

	int n_entries;

	enum port port = encoder->port;

	const struct ddi_buf_trans *ddi_translations;



	ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);

	const struct intel_ddi_buf_trans *ddi_translations;



	ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

		return;

	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
@@ -155,9 +149,9 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 


	/* Entry 9 is for HDMI: */

	intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),

		       ddi_translations[level].trans1 | iboost_bit);

		       ddi_translations->entries[level].hsw.trans1 | iboost_bit);

	intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),

		       ddi_translations[level].trans2);

		       ddi_translations->entries[level].hsw.trans2);

}



void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
@@ -948,22 +942,16 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, 
		iboost = intel_bios_encoder_dp_boost_level(encoder->devdata);



	if (iboost == 0) {

		const struct ddi_buf_trans *ddi_translations;

		const struct intel_ddi_buf_trans *ddi_translations;

		int n_entries;



		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

			ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);

		else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

			ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries);

		else

			ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries);



		ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);

		if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

			return;

		if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))

			level = n_entries - 1;



		iboost = ddi_translations[level].i_boost;

		iboost = ddi_translations->entries[level].hsw.i_boost;

	}



	/* Make sure that the requested I_boost is valid */
@@ -983,21 +971,21 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 
				    int level)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	const struct bxt_ddi_buf_trans *ddi_translations;

	const struct intel_ddi_buf_trans *ddi_translations;

	enum port port = encoder->port;

	int n_entries;



	ddi_translations = bxt_get_buf_trans(encoder, crtc_state, &n_entries);

	ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

		return;

	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))

		level = n_entries - 1;



	bxt_ddi_phy_set_signal_level(dev_priv, port,

				     ddi_translations[level].margin,

				     ddi_translations[level].scale,

				     ddi_translations[level].enable,

				     ddi_translations[level].deemphasis);

				     ddi_translations->entries[level].bxt.margin,

				     ddi_translations->entries[level].bxt.scale,

				     ddi_translations->entries[level].bxt.enable,

				     ddi_translations->entries[level].bxt.deemphasis);

}



static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
@@ -1005,36 +993,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 
{

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum port port = encoder->port;

	enum phy phy = intel_port_to_phy(dev_priv, port);

	int n_entries;



	if (DISPLAY_VER(dev_priv) >= 12) {

		if (intel_phy_is_combo(dev_priv, phy))

			tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);

		else if (IS_ALDERLAKE_P(dev_priv))

			adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);

		else

			tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);

	} else if (DISPLAY_VER(dev_priv) == 11) {

		if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))

			jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);

		else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))

			ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);

		else if (intel_phy_is_combo(dev_priv, phy))

			icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);

		else

			icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);

	} else if (IS_CANNONLAKE(dev_priv)) {

		cnl_get_buf_trans(encoder, crtc_state, &n_entries);

	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {

		bxt_get_buf_trans(encoder, crtc_state, &n_entries);

	} else {

		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

			intel_ddi_get_buf_trans_edp(encoder, &n_entries);

		else

			intel_ddi_get_buf_trans_dp(encoder, &n_entries);

	}

	encoder->get_buf_trans(encoder, crtc_state, &n_entries);



	if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))

		n_entries = 1;
@@ -1061,13 +1022,12 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 
				   int level)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	const struct cnl_ddi_buf_trans *ddi_translations;

	const struct intel_ddi_buf_trans *ddi_translations;

	enum port port = encoder->port;

	int n_entries, ln;

	u32 val;



	ddi_translations = cnl_get_buf_trans(encoder, crtc_state, &n_entries);



	ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

		return;

	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
@@ -1083,8 +1043,8 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 
	val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));

	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |

		 RCOMP_SCALAR_MASK);

	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);

	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);

	val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);

	val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);

	/* Rcomp scalar is fixed as 0x98 for every table entry */

	val |= RCOMP_SCALAR(0x98);

	intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
@@ -1095,9 +1055,9 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 
		val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));

		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |

			 CURSOR_COEFF_MASK);

		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);

		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);

		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);

		val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);

		val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);

		val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);

		intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);

	}
@@ -1112,7 +1072,7 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 
	/* Program PORT_TX_DW7 */

	val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));

	val &= ~N_SCALAR_MASK;

	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);

	val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);

	intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);

}
@@ -1182,20 +1142,12 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 
					 int level)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	const struct cnl_ddi_buf_trans *ddi_translations;

	const struct intel_ddi_buf_trans *ddi_translations;

	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);

	int n_entries, ln;

	u32 val;



	if (DISPLAY_VER(dev_priv) >= 12)

		ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);

	else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))

		ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);

	else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))

		ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);

	else

		ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);



	ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

		return;

	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
@@ -1223,8 +1175,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 
	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));

	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |

		 RCOMP_SCALAR_MASK);

	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);

	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);

	val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);

	val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);

	/* Program Rcomp scalar for every table entry */

	val |= RCOMP_SCALAR(0x98);

	intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
@@ -1235,16 +1187,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 
		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));

		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |

			 CURSOR_COEFF_MASK);

		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);

		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);

		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);

		val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);

		val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);

		val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);

		intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);

	}



	/* Program PORT_TX_DW7 */

	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));

	val &= ~N_SCALAR_MASK;

	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);

	val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);

	intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);

}
@@ -1315,15 +1267,14 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);

	const struct icl_mg_phy_ddi_buf_trans *ddi_translations;

	const struct intel_ddi_buf_trans *ddi_translations;

	int n_entries, ln;

	u32 val;



	if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)

		return;



	ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);



	ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

		return;

	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
@@ -1345,13 +1296,13 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 
		val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));

		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;

		val |= CRI_TXDEEMPH_OVERRIDE_17_12(

			ddi_translations[level].cri_txdeemph_override_17_12);

			ddi_translations->entries[level].mg.cri_txdeemph_override_17_12);

		intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);



		val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));

		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;

		val |= CRI_TXDEEMPH_OVERRIDE_17_12(

			ddi_translations[level].cri_txdeemph_override_17_12);

			ddi_translations->entries[level].mg.cri_txdeemph_override_17_12);

		intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);

	}
@@ -1361,9 +1312,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 
		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |

			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);

		val |= CRI_TXDEEMPH_OVERRIDE_5_0(

			ddi_translations[level].cri_txdeemph_override_5_0) |

			ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) |

			CRI_TXDEEMPH_OVERRIDE_11_6(

				ddi_translations[level].cri_txdeemph_override_11_6) |

				ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) |

			CRI_TXDEEMPH_OVERRIDE_EN;

		intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
@@ -1371,9 +1322,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 
		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |

			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);

		val |= CRI_TXDEEMPH_OVERRIDE_5_0(

			ddi_translations[level].cri_txdeemph_override_5_0) |

			ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) |

			CRI_TXDEEMPH_OVERRIDE_11_6(

				ddi_translations[level].cri_txdeemph_override_11_6) |

				ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) |

			CRI_TXDEEMPH_OVERRIDE_EN;

		intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
@@ -1453,18 +1404,14 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);

	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;

	const struct intel_ddi_buf_trans *ddi_translations;

	u32 val, dpcnt_mask, dpcnt_val;

	int n_entries, ln;



	if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)

		return;



	if (IS_ALDERLAKE_P(dev_priv))

		ddi_translations = adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);

	else

		ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);



	ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

		return;

	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
@@ -1473,9 +1420,9 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 
	dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |

		      DKL_TX_DE_EMPAHSIS_COEFF_MASK |

		      DKL_TX_VSWING_CONTROL_MASK);

	dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);

	dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);

	dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);

	dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations->entries[level].dkl.dkl_vswing_control);

	dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations->entries[level].dkl.dkl_de_emphasis_control);

	dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations->entries[level].dkl.dkl_preshoot_control);



	for (ln = 0; ln < 2; ln++) {

		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
@@ -2715,7 +2662,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 
	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))

		bxt_ddi_vswing_sequence(encoder, crtc_state, level);

	else

		intel_prepare_dp_ddi_buffers(encoder, crtc_state);

		hsw_prepare_dp_ddi_buffers(encoder, crtc_state);



	intel_ddi_power_up_lanes(encoder, crtc_state);
@@ -2823,6 +2770,7 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, 
					conn_state);



		/* FIXME precompute everything properly */

		/* FIXME how do we turn infoframes off again? */

		if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)

			dig_port->set_infoframes(encoder,

						 crtc_state->has_infoframe,
@@ -3162,7 +3110,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 
	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))

		bxt_ddi_vswing_sequence(encoder, crtc_state, level);

	else

		intel_prepare_hdmi_ddi_buffers(encoder, level);

		hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state, level);



	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))

		skl_ddi_set_iboost(encoder, crtc_state, level);
@@ -3590,7 +3538,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 
				    struct intel_crtc_state *pipe_config)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);

	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);

	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;

	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

	u32 temp, flags = 0;
@@ -3653,7 +3601,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 
			pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);

		pipe_config->lane_count =

			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;

		intel_dp_get_m_n(intel_crtc, pipe_config);

		intel_dp_get_m_n(crtc, pipe_config);



		if (DISPLAY_VER(dev_priv) >= 11) {

			i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
@@ -3683,7 +3631,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 
			pipe_config->mst_master_transcoder =

					REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);



		intel_dp_get_m_n(intel_crtc, pipe_config);

		intel_dp_get_m_n(crtc, pipe_config);



		pipe_config->infoframes.enable |=

			intel_hdmi_infoframes_enabled(encoder, pipe_config);
@@ -4509,6 +4457,36 @@ static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 
		return false;

}



static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)

{

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	enum phy phy = intel_port_to_phy(i915, encoder->port);



	intel_dp_encoder_suspend(encoder);



	if (!intel_phy_is_tc(i915, phy))

		return;



	intel_tc_port_disconnect_phy(dig_port);

}



static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)

{

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	enum phy phy = intel_port_to_phy(i915, encoder->port);



	intel_dp_encoder_shutdown(encoder);



	if (!intel_phy_is_tc(i915, phy))

		return;



	intel_tc_port_disconnect_phy(dig_port);

}



#define port_tc_name(port) ((port) - PORT_TC1 + '1')

#define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
@@ -4618,8 +4596,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 
	encoder->get_hw_state = intel_ddi_get_hw_state;

	encoder->sync_state = intel_ddi_sync_state;

	encoder->initial_fastset_check = intel_ddi_initial_fastset_check;

	encoder->suspend = intel_dp_encoder_suspend;

	encoder->shutdown = intel_dp_encoder_shutdown;

	encoder->suspend = intel_ddi_encoder_suspend;

	encoder->shutdown = intel_ddi_encoder_shutdown;

	encoder->get_power_domains = intel_ddi_get_power_domains;



	encoder->type = INTEL_OUTPUT_DDI;
@@ -4687,6 +4665,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 
		encoder->get_config = hsw_ddi_get_config;

	}



	intel_ddi_buf_trans_init(encoder);



	if (DISPLAY_VER(dev_priv) >= 13)

		encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);

	else if (IS_DG1(dev_priv))

drivers/gpu/drm/i915/display/intel_ddi.h

+2 −2
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder); 
void hsw_ddi_get_config(struct intel_encoder *encoder,

			struct intel_crtc_state *crtc_state);

struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);

void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,

void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,

				const struct intel_crtc_state *crtc_state);

void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,

			     enum port port);