Commit b4d36c10 authored by Richard Zhu's avatar Richard Zhu Committed by Shawn Guo
Browse files

arm64: dts: imx8mm-evk: Add the pcie support on imx8mm evk board 



Add the PCIe support on iMX8MM EVK boards.
And set the default reference clock mode.

Signed-off-by: default avatarRichard Zhu <hongxing.zhu@nxp.com>
Tested-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: default avatarTim Harvey <tharvey@gateworks.com>
Tested-by: default avatarTim Harvey <tharvey@gateworks.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent aaeba6a8

arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi

+55 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 


/dts-v1/;



#include <dt-bindings/phy/phy-imx8-pcie.h>

#include <dt-bindings/usb/pd.h>

#include "imx8mm.dtsi"
@@ -30,6 +31,23 @@ 
		};

	};



	pcie0_refclk: pcie0-refclk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <100000000>;

	};



	reg_pcie0: regulator-pcie {

		compatible = "regulator-fixed";

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_pcie0_reg>;

		regulator-name = "MPCIE_3V3";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	reg_usdhc2_vmmc: regulator-usdhc2 {

		compatible = "regulator-fixed";

		pinctrl-names = "default";
@@ -296,6 +314,30 @@ 
	};

};



&pcie_phy {

	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;

	fsl,tx-deemph-gen1 = <0x2d>;

	fsl,tx-deemph-gen2 = <0xf>;

	clocks = <&pcie0_refclk>;

	status = "okay";

};



&pcie0 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,

		 <&pcie0_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_bus";

	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,

			  <&clk IMX8MM_CLK_PCIE1_CTRL>;

	assigned-clock-rates = <10000000>, <250000000>;

	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,

				 <&clk IMX8MM_SYS_PLL2_250M>;

	vpcie-supply = <&reg_pcie0>;

	status = "okay";

};



&sai3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_sai3>;
@@ -413,6 +455,19 @@ 
		>;

	};



	pinctrl_pcie0: pcie0grp {

		fsl,pins = <

			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61

			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41

		>;

	};



	pinctrl_pcie0_reg: pcie0reggrp {

		fsl,pins = <

			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41

		>;

	};



	pinctrl_pmic: pmicirqgrp {

		fsl,pins = <

			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141