Commit b4bc93bd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM driver updates from Arnd Bergmann:
 "There are a few separately maintained driver subsystems that we merge
  through the SoC tree, notable changes are:

   - Memory controller updates, mainly for Tegra and Mediatek SoCs, and
     clarifications for the memory controller DT bindings

   - SCMI firmware interface updates, in particular a new transport
     based on OPTEE and support for atomic operations.

   - Cleanups to the TEE subsystem, refactoring its memory management

  For SoC specific drivers without a separate subsystem, changes include

   - Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP
     Layerscape SoCs.

   - Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L,
     and Qualcomm SM8450.

   - Better power management on Mediatek MT81xx, NXP i.MX8MQ and older
     NVIDIA Tegra chips"

* tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (154 commits)
  ARM: spear: fix typos in comments
  soc/microchip: fix invalid free in mpfs_sys_controller_delete
  soc: s4: Add support for power domains controller
  dt-bindings: power: add Amlogic s4 power domains bindings
  ARM: at91: add support in soc driver for new SAMA5D29
  soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
  dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC
  memory: emif: check the pointer temp in get_device_details()
  memory: emif: Add check for setup_interrupts
  dt-bindings: arm: mediatek: mmsys: add support for MT8186
  dt-bindings: mediatek: add compatible for MT8186 pwrap
  soc: mediatek: pwrap: add pwrap driver for MT8186 SoC
  soc: mediatek: mmsys: add mmsys reset control for MT8186
  soc: mediatek: mtk-infracfg: Disable ACP on MT8192
  soc: ti: k3-socinfo: Add AM62x JTAG ID
  soc: mediatek: add MTK mutex support for MT8186
  soc: mediatek: mmsys: add mt8186 mmsys routing table
  soc: mediatek: pm-domains: Add support for mt8186
  dt-bindings: power: Add MT8186 power domains
  soc: mediatek: pm-domains: Add support for mt8195
  ...
parents baaa68a9 339ac71b

Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml

+1 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ properties: 
              - mediatek,mt8167-mmsys

              - mediatek,mt8173-mmsys

              - mediatek,mt8183-mmsys

              - mediatek,mt8186-mmsys

              - mediatek,mt8192-mmsys

              - mediatek,mt8365-mmsys

          - const: syscon

Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml

+2 −0
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ properties: 
      - qcom,sm6350-llcc

      - qcom,sm8150-llcc

      - qcom,sm8250-llcc

      - qcom,sm8350-llcc

      - qcom,sm8450-llcc



  reg:

    items:

Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml

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+198 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Tesla FSD (Full Self-Driving) SoC clock controller



maintainers:

  - Alim Akhtar <alim.akhtar@samsung.com>

  - linux-fsd@tesla.com



description: |

  FSD clock controller consist of several clock management unit

  (CMU), which generates clocks for various inteernal SoC blocks.

  The root clock comes from external OSC clock (24 MHz).



  All available clocks are defined as preprocessor macros in

  'dt-bindings/clock/fsd-clk.h' header.



properties:

  compatible:

    enum:

      - tesla,fsd-clock-cmu

      - tesla,fsd-clock-imem

      - tesla,fsd-clock-peric

      - tesla,fsd-clock-fsys0

      - tesla,fsd-clock-fsys1

      - tesla,fsd-clock-mfc

      - tesla,fsd-clock-cam_csi



  clocks:

    minItems: 1

    maxItems: 6



  clock-names:

    minItems: 1

    maxItems: 6



  "#clock-cells":

    const: 1



  reg:

    maxItems: 1



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: tesla,fsd-clock-cmu

    then:

      properties:

        clocks:

          items:

            - description: External reference clock (24 MHz)

        clock-names:

          items:

            - const: fin_pll



  - if:

      properties:

        compatible:

          contains:

            const: tesla,fsd-clock-imem

    then:

      properties:

        clocks:

          items:

            - description: External reference clock (24 MHz)

            - description: IMEM TCU clock (from CMU_CMU)

            - description: IMEM bus clock (from CMU_CMU)

            - description: IMEM DMA clock (from CMU_CMU)

        clock-names:

          items:

            - const: fin_pll

            - const: dout_cmu_imem_tcuclk

            - const: dout_cmu_imem_aclk

            - const: dout_cmu_imem_dmaclk



  - if:

      properties:

        compatible:

          contains:

            const: tesla,fsd-clock-peric

    then:

      properties:

        clocks:

          items:

            - description: External reference clock (24 MHz)

            - description: Shared0 PLL div4 clock (from CMU_CMU)

            - description: PERIC shared1 div36 clock (from CMU_CMU)

            - description: PERIC shared0 div3 TBU clock (from CMU_CMU)

            - description: PERIC shared0 div20 clock (from CMU_CMU)

            - description: PERIC shared1 div4 DMAclock (from CMU_CMU)

        clock-names:

          items:

            - const: fin_pll

            - const: dout_cmu_pll_shared0_div4

            - const: dout_cmu_peric_shared1div36

            - const: dout_cmu_peric_shared0div3_tbuclk

            - const: dout_cmu_peric_shared0div20

            - const: dout_cmu_peric_shared1div4_dmaclk



  - if:

      properties:

        compatible:

          contains:

            const: tesla,fsd-clock-fsys0

    then:

      properties:

        clocks:

          items:

            - description: External reference clock (24 MHz)

            - description: Shared0 PLL div6 clock (from CMU_CMU)

            - description: FSYS0 shared1 div4 clock (from CMU_CMU)

            - description: FSYS0 shared0 div4 clock (from CMU_CMU)

        clock-names:

          items:

            - const: fin_pll

            - const: dout_cmu_pll_shared0_div6

            - const: dout_cmu_fsys0_shared1div4

            - const: dout_cmu_fsys0_shared0div4



  - if:

      properties:

        compatible:

          contains:

            const: tesla,fsd-clock-fsys1

    then:

      properties:

        clocks:

          items:

            - description: External reference clock (24 MHz)

            - description: FSYS1 shared0 div8 clock (from CMU_CMU)

            - description: FSYS1 shared0 div4 clock (from CMU_CMU)

        clock-names:

          items:

            - const: fin_pll

            - const: dout_cmu_fsys1_shared0div8

            - const: dout_cmu_fsys1_shared0div4



  - if:

      properties:

        compatible:

          contains:

            const: tesla,fsd-clock-mfc

    then:

      properties:

        clocks:

          items:

            - description: External reference clock (24 MHz)

        clock-names:

          items:

            - const: fin_pll



  - if:

      properties:

        compatible:

          contains:

            const: tesla,fsd-clock-cam_csi

    then:

      properties:

        clocks:

          items:

            - description: External reference clock (24 MHz)

        clock-names:

          items:

            - const: fin_pll



required:

  - compatible

  - "#clock-cells"

  - clocks

  - clock-names

  - reg



additionalProperties: false



examples:

  # Clock controller node for CMU_FSYS1

  - |

    #include <dt-bindings/clock/fsd-clk.h>



    clock_fsys1: clock-controller@16810000 {

          compatible = "tesla,fsd-clock-fsys1";

          reg = <0x16810000 0x3000>;

          #clock-cells = <1>;



          clocks = <&fin_pll>,

                   <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,

                   <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;

          clock-names = "fin_pll",

                        "dout_cmu_fsys1_shared0div8",

                        "dout_cmu_fsys1_shared0div4";

    };



...

Documentation/devicetree/bindings/firmware/arm,scmi.yaml

+75 −0
Original line number Diff line number Diff line
@@ -38,6 +38,9 @@ properties: 
                     The virtio transport only supports a single device.

        items:

          - const: arm,scmi-virtio

      - description: SCMI compliant firmware with OP-TEE transport

        items:

          - const: linaro,scmi-optee



  interrupts:

    description:
@@ -78,11 +81,24 @@ properties: 
  '#size-cells':

    const: 0



  atomic-threshold-us:

    description:

      An optional time value, expressed in microseconds, representing, on this

      platform, the threshold above which any SCMI command, advertised to have

      an higher-than-threshold execution latency, should not be considered for

      atomic mode of operation, even if requested.

    default: 0



  arm,smc-id:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      SMC id required when using smc or hvc transports



  linaro,optee-channel-id:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Channel specifier required when using OP-TEE transport.



  protocol@11:

    type: object

    properties:
@@ -195,6 +211,12 @@ patternProperties: 
        minItems: 1

        maxItems: 2



      linaro,optee-channel-id:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Channel specifier required when using OP-TEE transport and

          protocol has a dedicated communication channel.



    required:

      - reg
@@ -226,6 +248,16 @@ else: 
      - arm,smc-id

      - shmem



  else:

    if:

      properties:

        compatible:

          contains:

            const: linaro,scmi-optee

    then:

      required:

        - linaro,optee-channel-id



examples:

  - |

    firmware {
@@ -240,6 +272,8 @@ examples: 
            #address-cells = <1>;

            #size-cells = <0>;



            atomic-threshold-us = <10000>;



            scmi_devpd: protocol@11 {

                reg = <0x11>;

                #power-domain-cells = <1>;
@@ -340,7 +374,48 @@ examples: 
                reg = <0x11>;

                #power-domain-cells = <1>;

            };

        };

    };



  - |

    firmware {

        scmi {

            compatible = "linaro,scmi-optee";

            linaro,optee-channel-id = <0>;



            #address-cells = <1>;

            #size-cells = <0>;



            scmi_dvfs1: protocol@13 {

                reg = <0x13>;

                linaro,optee-channel-id = <1>;

                shmem = <&cpu_optee_lpri0>;

                #clock-cells = <1>;

            };



            scmi_clk0: protocol@14 {

                reg = <0x14>;

                #clock-cells = <1>;

            };

        };

    };



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        sram@51000000 {

            compatible = "mmio-sram";

            reg = <0x0 0x51000000 0x0 0x10000>;



            #address-cells = <1>;

            #size-cells = <1>;

            ranges = <0 0x0 0x51000000 0x10000>;



            cpu_optee_lpri0: optee-sram-section@0 {

                compatible = "arm,scmi-shmem";

                reg = <0x0 0x80>;

            };

        };

    };

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml

0 → 100644
+135 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: LPDDR2 SDRAM AC timing parameters for a given speed-bin



maintainers:

  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>



properties:

  compatible:

    const: jedec,lpddr2-timings



  max-freq:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Maximum DDR clock frequency for the speed-bin, in Hz.



  min-freq:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Minimum DDR clock frequency for the speed-bin, in Hz.



  tCKESR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      CKE minimum pulse width during SELF REFRESH (low pulse width during

      SELF REFRESH) in pico seconds.



  tDQSCK-max:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      DQS output data access time from CK_t/CK_c in pico seconds.



  tDQSCK-max-derated:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      DQS output data access time from CK_t/CK_c, temperature de-rated, in pico

      seconds.



  tFAW:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Four-bank activate window in pico seconds.



  tRAS-max-ns:

    description: |

      Row active time in nano seconds.



  tRAS-min:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Row active time in pico seconds.



  tRCD:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      RAS-to-CAS delay in pico seconds.



  tRPab:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Row precharge time (all banks) in pico seconds.



  tRRD:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Active bank A to active bank B in pico seconds.



  tRTP:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Internal READ to PRECHARGE command delay in pico seconds.



  tWR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      WRITE recovery time in pico seconds.



  tWTR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Internal WRITE-to-READ command delay in pico seconds.



  tXP:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Exit power-down to next valid command delay in pico seconds.



  tZQCL:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Long calibration time in pico seconds.



  tZQCS:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Short calibration time in pico seconds.



  tZQinit:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Initialization calibration time in pico seconds.



required:

  - compatible

  - min-freq

  - max-freq



additionalProperties: false



examples:

  - |

    timings {

        compatible = "jedec,lpddr2-timings";

        min-freq = <10000000>;

        max-freq = <400000000>;

        tCKESR = <15000>;

        tDQSCK-max = <5500>;

        tFAW = <50000>;

        tRAS-max-ns = <70000>;

        tRAS-min = <42000>;

        tRPab = <21000>;

        tRCD = <18000>;

        tRRD = <10000>;

        tRTP = <7500>;

        tWR = <15000>;

        tWTR = <7500>;

        tXP = <7500>;

        tZQCL = <360000>;

        tZQCS = <90000>;

        tZQinit = <1000000>;

    };