Commit b4b02524 authored by Conor Dooley's avatar Conor Dooley Committed by Claudiu Beznea
Browse files

dt-bindings: clk: add PolarFire SoC fabric clock ids 

Each Clock Conditioning Circuitry block contains 2 PLLs and 2 DLLs.
The PLLs have 4 outputs each and the DLLs 2. Add 16 new IDs covering
these clocks. For more information on the CCC hardware, see the
"PolarFire SoC FPGA Clocking Resources" document at the link below.

Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html


Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908143651.1252601-4-conor.dooley@microchip.com
parent 3ffb5ad2

include/dt-bindings/clock/microchip,mpfs-clock.h

+23 −0
Original line number Diff line number Diff line
@@ -45,4 +45,27 @@ 
#define CLK_RTCREF	33

#define CLK_MSSPLL	34



/* Clock Conditioning Circuitry Clock IDs */



#define CLK_CCC_PLL0		0

#define CLK_CCC_PLL1		1

#define CLK_CCC_DLL0		2

#define CLK_CCC_DLL1		3



#define CLK_CCC_PLL0_OUT0	4

#define CLK_CCC_PLL0_OUT1	5

#define CLK_CCC_PLL0_OUT2	6

#define CLK_CCC_PLL0_OUT3	7



#define CLK_CCC_PLL1_OUT0	8

#define CLK_CCC_PLL1_OUT1	9

#define CLK_CCC_PLL1_OUT2	10

#define CLK_CCC_PLL1_OUT3	11



#define CLK_CCC_DLL0_OUT0	12

#define CLK_CCC_DLL0_OUT1	13



#define CLK_CCC_DLL1_OUT0	14

#define CLK_CCC_DLL1_OUT1	15



#endif	/* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */