Unverified Commit b49aae5e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v6.0-next-soc' of... 

Merge tag 'v6.0-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

pmic-wrapper:
- add support for mt8188

SVS:
- several driver cleanups

power-domain:
- several cleanups of the dt-bindings and driver

mutex:
- add support to mt6795 disp mutex
- add support for mt8186 mdp3 mutex

* tag 'v6.0-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  soc: mediatek: Add mmsys func to adapt to dpi output for MT8186
  soc: mediatek: mutex: Add support for MT6795 Helio X10 display mutex
  dt-bindings: soc: mediatek: Add display mutex support for MT6795
  soc: mediatek: mutex: Add mt8186 mutex mod settings for mdp3
  dt-bindings: soc: mediatek: Add mdp3 mutex support for mt8186
  soc: mediatek: pm-domains: Simplify some error message
  soc: mediatek: mtk-svs: Explicitly include bitfield header
  soc: mediatek: mtk-svs: Use bitfield access macros where possible
  soc: mediatek: mtk-svs: Commonize t-calibration-data fuse array read
  dt-bindings: power: mediatek: Update maintainer list
  dt-bindings: power: mediatek: Support naming power controller node with unit address
  dt-bindings: power: mediatek: Refine multiple level power domain nodes
  soc: mediatek: mtk-svs: Use devm variant for dev_pm_opp_of_add_table()
  soc: mediatek: mtk-svs: Drop of_match_ptr() for of_match_table
  soc: mediatek: mtk-svs: Remove hardcoded irqflags
  soc: mediatek: mtk-svs: Switch to platform_get_irq()
  dt-bindings: soc: mediatek: pwrap: add compatible for mt8188
  soc: mediatek: Let PMIC Wrapper and SCPSYS depend on OF

Link: https://lore.kernel.org/r/498fe3e5-a237-121a-d500-fbb0994906cb@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 891518b7 b404cb45

Documentation/devicetree/bindings/power/mediatek,power-controller.yaml

+19 −116
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Mediatek Power Domains Controller



maintainers:

  - Weiyi Lu <weiyi.lu@mediatek.com>

  - MandyJH Liu <mandyjh.liu@mediatek.com>

  - Matthias Brugger <mbrugger@suse.com>



description: |
@@ -19,7 +19,7 @@ description: | 


properties:

  $nodename:

    const: power-controller

    pattern: '^power-controller(@[0-9a-f]+)?$'



  compatible:

    enum:
@@ -42,6 +42,23 @@ properties: 


patternProperties:

  "^power-domain@[0-9a-f]+$":

    $ref: "#/$defs/power-domain-node"

    patternProperties:

      "^power-domain@[0-9a-f]+$":

        $ref: "#/$defs/power-domain-node"

        patternProperties:

          "^power-domain@[0-9a-f]+$":

            $ref: "#/$defs/power-domain-node"

            patternProperties:

              "^power-domain@[0-9a-f]+$":

                $ref: "#/$defs/power-domain-node"

                unevaluatedProperties: false

            unevaluatedProperties: false

        unevaluatedProperties: false

    unevaluatedProperties: false



$defs:

  power-domain-node:

    type: object

    description: |

      Represents the power domains within the power controller node as documented
@@ -100,123 +117,9 @@ patternProperties: 
        $ref: /schemas/types.yaml#/definitions/phandle

        description: phandle to the device containing the SMI register range.



    patternProperties:

      "^power-domain@[0-9a-f]+$":

        type: object

        description: |

          Represents a power domain child within a power domain parent node.



        properties:



          '#power-domain-cells':

            description:

              Must be 0 for nodes representing a single PM domain and 1 for nodes

              providing multiple PM domains.



          '#address-cells':

            const: 1



          '#size-cells':

            const: 0



          reg:

            maxItems: 1



          clocks:

            description: |

              A number of phandles to clocks that need to be enabled during domain

              power-up sequencing.



          clock-names:

            description: |

              List of names of clocks, in order to match the power-up sequencing

              for each power domain we need to group the clocks by name. BASIC

              clocks need to be enabled before enabling the corresponding power

              domain, and should not have a '-' in their name (i.e mm, mfg, venc).

              SUSBYS clocks need to be enabled before releasing the bus protection,

              and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).



              In order to follow properly the power-up sequencing, the clocks must

              be specified by order, adding first the BASIC clocks followed by the

              SUSBSYS clocks.



          domain-supply:

            description: domain regulator supply.



          mediatek,infracfg:

            $ref: /schemas/types.yaml#/definitions/phandle

            description: phandle to the device containing the INFRACFG register range.



          mediatek,smi:

            $ref: /schemas/types.yaml#/definitions/phandle

            description: phandle to the device containing the SMI register range.



        patternProperties:

          "^power-domain@[0-9a-f]+$":

            type: object

            description: |

              Represents a power domain child within a power domain parent node.



            properties:



              '#power-domain-cells':

                description:

                  Must be 0 for nodes representing a single PM domain and 1 for nodes

                  providing multiple PM domains.



              '#address-cells':

                const: 1



              '#size-cells':

                const: 0



              reg:

                maxItems: 1



              clocks:

                description: |

                  A number of phandles to clocks that need to be enabled during domain

                  power-up sequencing.



              clock-names:

                description: |

                  List of names of clocks, in order to match the power-up sequencing

                  for each power domain we need to group the clocks by name. BASIC

                  clocks need to be enabled before enabling the corresponding power

                  domain, and should not have a '-' in their name (i.e mm, mfg, venc).

                  SUSBYS clocks need to be enabled before releasing the bus protection,

                  and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).



                  In order to follow properly the power-up sequencing, the clocks must

                  be specified by order, adding first the BASIC clocks followed by the

                  SUSBSYS clocks.



              domain-supply:

                description: domain regulator supply.



              mediatek,infracfg:

                $ref: /schemas/types.yaml#/definitions/phandle

                description: phandle to the device containing the INFRACFG register range.



              mediatek,smi:

                $ref: /schemas/types.yaml#/definitions/phandle

                description: phandle to the device containing the SMI register range.



            required:

              - reg



            additionalProperties: false



    required:

      - reg



        additionalProperties: false



    required:

      - reg



    additionalProperties: false



required:

  - compatible

Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml

+2 −0
Original line number Diff line number Diff line
@@ -26,10 +26,12 @@ properties: 
    enum:

      - mediatek,mt2701-disp-mutex

      - mediatek,mt2712-disp-mutex

      - mediatek,mt6795-disp-mutex

      - mediatek,mt8167-disp-mutex

      - mediatek,mt8173-disp-mutex

      - mediatek,mt8183-disp-mutex

      - mediatek,mt8186-disp-mutex

      - mediatek,mt8186-mdp3-mutex

      - mediatek,mt8192-disp-mutex

      - mediatek,mt8195-disp-mutex

Documentation/devicetree/bindings/soc/mediatek/pwrap.txt

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ Required properties in pwrap device node. 
	"mediatek,mt8173-pwrap" for MT8173 SoCs

	"mediatek,mt8183-pwrap" for MT8183 SoCs

	"mediatek,mt8186-pwrap" for MT8186 SoCs

	"mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs

	"mediatek,mt8195-pwrap" for MT8195 SoCs

	"mediatek,mt8516-pwrap" for MT8516 SoCs

- interrupts: IRQ for pwrap in SOC

drivers/soc/mediatek/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ config MTK_INFRACFG 
config MTK_PMIC_WRAP

	tristate "MediaTek PMIC Wrapper Support"

	depends on RESET_CONTROLLER

	depends on OF

	select REGMAP

	help

	  Say yes here to add support for MediaTek PMIC Wrapper found
@@ -46,6 +47,7 @@ config MTK_PMIC_WRAP 
config MTK_SCPSYS

	bool "MediaTek SCPSYS Support"

	default ARCH_MEDIATEK

	depends on OF

	select REGMAP

	select MTK_INFRACFG

	select PM_GENERIC_DOMAINS if PM

drivers/soc/mediatek/mt8186-mmsys.h

+6 −0
Original line number Diff line number Diff line
@@ -3,6 +3,12 @@ 
#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H

#define __SOC_MEDIATEK_MT8186_MMSYS_H



/* Values for DPI configuration in MMSYS address space */

#define MT8186_MMSYS_DPI_OUTPUT_FORMAT		0x400

#define DPI_FORMAT_MASK					0x1

#define DPI_RGB888_DDR_CON				BIT(0)

#define DPI_RGB565_SDR_CON				BIT(1)



#define MT8186_MMSYS_OVL_CON			0xF04

#define MT8186_MMSYS_OVL0_CON_MASK			0x3

#define MT8186_MMSYS_OVL0_2L_CON_MASK			0xC