Commit b46a22de authored by Cristian Ciocaltea's avatar Cristian Ciocaltea Committed by Heiko Stuebner
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arm64: dts: rockchip: Assign PLL_PPLL clock rate to 1.1 GHz on rk3588s 



The clock rate for PLL_PPLL has been wrongly initialized to 100 MHz
instead of 1.1 GHz. Fix it.

Fixes: c9211fa2 ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
Reported-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: default avatarCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20230402095054.384739-3-cristian.ciocaltea@collabora.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 87810bda

arch/arm64/boot/dts/rockchip/rk3588s.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -416,7 +416,7 @@ 
			<&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,

			<&cru CLK_GPU>;

		assigned-clock-rates =

			<100000000>, <786432000>,

			<1100000000>, <786432000>,

			<850000000>, <1188000000>,

			<702000000>,

			<400000000>, <500000000>,