Commit b4591268 authored by leoliu-oc's avatar leoliu-oc
Browse files

x86/delay: add support for Zhaoxin ZXPAUSE instruction 

zhaoxin inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8WZM0


CVE: NA

-----------------

ZXPAUSE instructs the processor to enter an implementation-dependent
optimized state. The instruction execution wakes up when the time-stamp
counter reaches or exceeds the implicit EDX:EAX 64-bit input value.
The instruction execution also wakes up due to the expiration of
the operating system time-limit or by an external interrupt.

ZXPAUSE is available on processors with X86_FEATURE_ZXPAUSE.
ZXPAUSE allows the processor to enter a light-weight power/performance
optimized state (C0.1 state) for a period specified by the instruction
or until the system time limit.

MSR_ZX_PAUSE_CONTROL MSR register allows the OS to enable/disable C0.2 on
the processor and to set the maximum time the processor can reside in C0.1
or C0.2. By default C0.2 is disabled.

A sysfs interface to adjust the time and the C0.2 enablement is provided in
a follow up change.

Signed-off-by: default avatarleoliu-oc <leoliu-oc@zhaoxin.com>
parent 8c0dfc8b

arch/x86/include/asm/cpufeature.h

+5 −2
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ enum cpuid_leafs 
	CPUID_RESERVED_7,

	CPUID_RESERVED_8,

	CPUID_RESERVED_9,

	CPUID_C000_0006_EAX,

};



#define X86_CAP_FMT_NUM "%d:%d"
@@ -111,8 +112,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 27, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 28, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 29, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 30, feature_bit) ||	\

	   REQUIRED_MASK_CHECK					  ||	\

	   BUILD_BUG_ON_ZERO(NCAPINTS != 30))

	   BUILD_BUG_ON_ZERO(NCAPINTS != 31))



#define DISABLED_MASK_BIT_SET(feature_bit)				\

	 ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  0, feature_bit) ||	\
@@ -145,8 +147,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 27, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 28, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 29, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 30, feature_bit) ||	\

	   DISABLED_MASK_CHECK					  ||	\

	   BUILD_BUG_ON_ZERO(NCAPINTS != 30))

	   BUILD_BUG_ON_ZERO(NCAPINTS != 31))



#define cpu_has(c, bit)							\

	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :	\

arch/x86/include/asm/cpufeatures.h

+4 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
/*

 * Defines x86 CPU feature bits

 */

#define NCAPINTS			30	   /* N 32-bit words worth of info */

#define NCAPINTS			31	   /* N 32-bit words worth of info */

#define NBUGINTS			4	   /* N 32-bit bug flags */



/*
@@ -487,6 +487,9 @@ 
#define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* "" BHI_DIS_S HW control enabled */

#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */



/* VIA/Cyrix/Centaur/Zhaoxin-defined CPU features, CPUID level 0xC0000006, word 21 */

#define X86_FEATURE_ZXPAUSE		(30*32 + 0) /* Zhaoxin ZXPAUSE */



/*

 * BUG word(s)

 */

arch/x86/include/asm/delay.h

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


void __init use_tsc_delay(void);

void __init use_tpause_delay(void);

void __init use_zxpause_delay(void);

void use_mwaitx_delay(void);



#endif /* _ASM_X86_DELAY_H */

arch/x86/include/asm/disabled-features.h

+2 −1
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@ 
#define DISABLED_MASK27	0

#define DISABLED_MASK28	0

#define DISABLED_MASK29	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 30)

#define DISABLED_MASK30	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 31)



#endif /* _ASM_X86_DISABLED_FEATURES_H */

arch/x86/include/asm/msr-index.h

+11 −0
Original line number Diff line number Diff line
@@ -75,12 +75,23 @@ 
#define MSR_IA32_UMWAIT_CONTROL			0xe1

#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE	BIT(0)

#define MSR_IA32_UMWAIT_CONTROL_RESERVED	BIT(1)



#define MSR_ZX_PAUSE_CONTROL			0x187f

#define MSR_ZX_PAUSE_CONTROL_C02_DISABLE	BIT(0)

#define MSR_ZX_PAUSE_CONTROL_RESERVED		BIT(1)



/*

 * The time field is bit[31:2], but representing a 32bit value with

 * bit[1:0] zero.

 */

#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK	(~0x03U)



/*

 * The time field is bit[31:2], but representing a 32bit value with

 * bit[1:0] zero.

 */

#define MSR_ZX_PAUSE_CONTROL_TIME_MASK		(~0x03U)



/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */

#define MSR_IA32_CORE_CAPS			  0x000000cf

#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT	  2