Commit b452dfe9 authored by Chris Brandt's avatar Chris Brandt Committed by Geert Uytterhoeven
Browse files

clk: renesas: rz: Select EXTAL vs USB clock 



Check the MD_CLK pin to determine the current clock mode in order to set
the pll clock parent correctly.

Signed-off-by: default avatarChris Brandt <chris.brandt@renesas.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 07496981

drivers/clk/renesas/clk-rz.c

+22 −2
Original line number Diff line number Diff line
@@ -25,10 +25,31 @@ struct rz_cpg { 
#define CPG_FRQCR	0x10

#define CPG_FRQCR2	0x14



#define PPR0		0xFCFE3200

#define PIBC0		0xFCFE7000



#define MD_CLK(x)	((x >> 2) & 1)	/* P0_2 */



/* -----------------------------------------------------------------------------

 * Initialization

 */



static u16 __init rz_cpg_read_mode_pins(void)

{

	void __iomem *ppr0, *pibc0;

	u16 modes;



	ppr0 = ioremap_nocache(PPR0, 2);

	pibc0 = ioremap_nocache(PIBC0, 2);

	BUG_ON(!ppr0 || !pibc0);

	iowrite16(4, pibc0);	/* enable input buffer */

	modes = ioread16(ppr0);

	iounmap(ppr0);

	iounmap(pibc0);



	return modes;

}



static struct clk * __init

rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)

{
@@ -37,8 +58,7 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na 
	static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };



	if (strcmp(name, "pll") == 0) {

		/* FIXME: cpg_mode should be read from GPIO. But no GPIO support yet */

		unsigned cpg_mode = 0; /* hardcoded to EXTAL for now */

		unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());

		const char *parent_name = of_clk_get_parent_name(np, cpg_mode);



		mult = cpg_mode ? (32 / 4) : 30;