Commit b4496b54 authored by Jiaxun Yang's avatar Jiaxun Yang Committed by Wen Zhiwei
Browse files

MIPS: mipsregs: Set proper ISA level for virt extensions 

stable inclusion
from stable-v6.6.69
commit 1258986bbd17954c674562971ad9a01171ff2127
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IBNEPJ

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=1258986bbd17954c674562971ad9a01171ff2127



--------------------------------

[ Upstream commit a640d6762a7d404644201ebf6d2a078e8dc84f97 ]

c994a3ec ("MIPS: set mips32r5 for virt extensions") setted
some instructions in virt extensions to ISA level mips32r5.

However TLB related vz instructions was leftover, also this
shouldn't be done to a R5 or R6 kernel buid.

Reorg macros to set ISA level as needed when _ASM_SET_VIRT
is called.

Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: default avatarWangYuli <wangyuli@uniontech.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarWen Zhiwei <wenzhiwei@kylinos.cn>
parent ebc5050b

arch/mips/include/asm/mipsregs.h

+8 −5
Original line number Diff line number Diff line
@@ -2078,7 +2078,14 @@ do { \ 
		_ASM_INSN_IF_MIPS(0x4200000c)				\

		_ASM_INSN32_IF_MM(0x0000517c)

#else	/* !TOOLCHAIN_SUPPORTS_VIRT */

#define _ASM_SET_VIRT ".set\tvirt\n\t"

#if MIPS_ISA_REV >= 5

#define _ASM_SET_VIRT_ISA

#elif defined(CONFIG_64BIT)

#define _ASM_SET_VIRT_ISA ".set\tmips64r5\n\t"

#else

#define _ASM_SET_VIRT_ISA ".set\tmips32r5\n\t"

#endif

#define _ASM_SET_VIRT _ASM_SET_VIRT_ISA ".set\tvirt\n\t"

#define _ASM_SET_MFGC0	_ASM_SET_VIRT

#define _ASM_SET_DMFGC0	_ASM_SET_VIRT

#define _ASM_SET_MTGC0	_ASM_SET_VIRT
@@ -2099,7 +2106,6 @@ do { \ 
({ int __res;								\

	__asm__ __volatile__(						\

		".set\tpush\n\t"					\

		".set\tmips32r5\n\t"					\

		_ASM_SET_MFGC0						\

		"mfgc0\t%0, " #source ", %1\n\t"			\

		_ASM_UNSET_MFGC0					\
@@ -2113,7 +2119,6 @@ do { \ 
({ unsigned long long __res;						\

	__asm__ __volatile__(						\

		".set\tpush\n\t"					\

		".set\tmips64r5\n\t"					\

		_ASM_SET_DMFGC0						\

		"dmfgc0\t%0, " #source ", %1\n\t"			\

		_ASM_UNSET_DMFGC0					\
@@ -2127,7 +2132,6 @@ do { \ 
do {									\

	__asm__ __volatile__(						\

		".set\tpush\n\t"					\

		".set\tmips32r5\n\t"					\

		_ASM_SET_MTGC0						\

		"mtgc0\t%z0, " #register ", %1\n\t"			\

		_ASM_UNSET_MTGC0					\
@@ -2140,7 +2144,6 @@ do { \ 
do {									\

	__asm__ __volatile__(						\

		".set\tpush\n\t"					\

		".set\tmips64r5\n\t"					\

		_ASM_SET_DMTGC0						\

		"dmtgc0\t%z0, " #register ", %1\n\t"			\

		_ASM_UNSET_DMTGC0					\