Commit b43a5442 authored by Zhengjun Xing's avatar Zhengjun Xing Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update event list for Snowridgex 

More uncore events are added in the converter tool:

https://github.com/intel/event-converter-for-linux-perf

Keep both alias and the original name for the events, in case someone
already used the alias in their script.

Generate the perf events based on Snowridgex(SNR) event list v1.20:

https://download.01.org/perfmon/SNR/



Signed-off-by: default avatarXing Zhengjun <zhengjun.xing@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220609094222.2030167-2-zhengjun.xing@linux.intel.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 9146af44

tools/perf/pmu-events/arch/x86/snowridgex/cache.json

+31 −29
Original line number Diff line number Diff line
@@ -5,20 +5,20 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x31",

        "EventName": "CORE_REJECT_L2Q.ANY",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event).  Counts on a per core basis.",

        "SampleAfterValue": "200003"

    },

    {

        "BriefDescription": "Counts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetches.",

        "BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x51",

        "EventName": "DL1.DIRTY_EVICTION",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetches.  Does not count evictions or dirty writebacks caused by snoops.  Does not count a replacement unless a (dirty) line was written back.",

        "PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.  Does not count evictions or dirty writebacks caused by snoops.  Does not count a replacement unless a (dirty) line was written back.",

        "SampleAfterValue": "200003",

        "UMask": "0x1"

    },
@@ -28,7 +28,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_XQ.ANY",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link.  The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).",

        "SampleAfterValue": "200003"
@@ -39,7 +39,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_REQUEST.ALL",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only.  Counts on a per core basis.",

        "SampleAfterValue": "200003"
@@ -50,7 +50,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_REQUEST.HIT",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.",

        "SampleAfterValue": "200003",
@@ -62,7 +62,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_REQUEST.MISS",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis.",

        "SampleAfterValue": "200003",
@@ -74,7 +74,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_REQUEST.REJECTS",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of L2 Cache accesses that miss the L2 and get BBL reject  short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis.",

        "SampleAfterValue": "200003",
@@ -86,9 +86,9 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.MISS",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",

        "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",

        "SampleAfterValue": "200003",

        "UMask": "0x41"

    },
@@ -98,7 +98,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.REFERENCE",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",

        "SampleAfterValue": "200003",
@@ -120,9 +120,9 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of cycles a core is stalled due to an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (non-DRAM).",

        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",

        "SampleAfterValue": "200003",

        "UMask": "0x20"

    },
@@ -132,9 +132,9 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache.",

        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",

        "SampleAfterValue": "200003",

        "UMask": "0x8"

    },
@@ -144,9 +144,9 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",

        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",

        "SampleAfterValue": "200003",

        "UMask": "0x10"

    },
@@ -166,7 +166,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x4"
@@ -177,7 +177,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x1"
@@ -188,25 +188,25 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",

        "SampleAfterValue": "200003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Counts the number of cycles a core is stalled due to a store buffer being full.",

        "BriefDescription": "Counts the number of cycles the core is stalled due to a store buffer being full.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x40"

    },

    {

        "BriefDescription": "Counts the number of load ops retired that hit in DRAM.",

        "BriefDescription": "Counts the number of load uops retired that hit in DRAM.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "Data_LA": "1",
@@ -218,7 +218,7 @@ 
        "UMask": "0x80"

    },

    {

        "BriefDescription": "Counts the number of retired loads that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core.",

        "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "Data_LA": "1",
@@ -281,6 +281,7 @@ 
        "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "Data_LA": "1",

        "EventCode": "0xd1",

        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",

        "PEBS": "1",
@@ -289,7 +290,7 @@ 
        "UMask": "0x4"

    },

    {

        "BriefDescription": "Counts the number of memory uops retired.  A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)",

        "BriefDescription": "Counts the number of memory uops retired.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "Data_LA": "1",
@@ -297,6 +298,7 @@ 
        "EventName": "MEM_UOPS_RETIRED.ALL",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of memory uops retired.  A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)",

        "SampleAfterValue": "200003",

        "UMask": "0x83"

    },
@@ -351,7 +353,7 @@ 
        "UMask": "0x43"

    },

    {

        "BriefDescription": "Counts the number of retired split loads uops.",

        "BriefDescription": "Counts the number of retired split load uops.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "Data_LA": "1",
@@ -1128,7 +1130,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x71",

        "EventName": "TOPDOWN_FE_BOUND.ICACHE",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "UMask": "0x20"

tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json

+5 −4
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the number of cycles the floating point divider is busy.  Does not imply a stall waiting for the divider.",

        "BriefDescription": "Counts the number of cycles the floating point divider is busy.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xcd",

        "EventName": "CYCLES_DIV_BUSY.FPDIV",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of cycles the floating point divider is busy.  Does not imply a stall waiting for the divider.",

        "SampleAfterValue": "200003",

        "UMask": "0x2"

    },
@@ -16,7 +17,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.FP_ASSIST",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",

        "SampleAfterValue": "20003",

tools/perf/pmu-events/arch/x86/snowridgex/frontend.json

+10 −10
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0xe6",

        "EventName": "BACLEARS.ANY",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend.  Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",

        "SampleAfterValue": "200003",
@@ -17,7 +17,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0xe6",

        "EventName": "BACLEARS.COND",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x10"
@@ -28,7 +28,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0xe6",

        "EventName": "BACLEARS.INDIRECT",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x2"
@@ -39,7 +39,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0xe6",

        "EventName": "BACLEARS.RETURN",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x8"
@@ -50,7 +50,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0xe6",

        "EventName": "BACLEARS.UNCOND",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x4"
@@ -61,7 +61,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0xe9",

        "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x1"
@@ -72,7 +72,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "ICACHE.ACCESSES",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the total number of requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",

        "SampleAfterValue": "200003",
@@ -84,7 +84,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "ICACHE.HIT",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of requests that hit in the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",

        "SampleAfterValue": "200003",
@@ -96,7 +96,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "ICACHE.MISSES",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of missed requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",

        "SampleAfterValue": "200003",

tools/perf/pmu-events/arch/x86/snowridgex/memory.json

+2 −2
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "20003",

        "UMask": "0x2"

tools/perf/pmu-events/arch/x86/snowridgex/other.json

+9 −9
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 
        "EdgeDetect": "1",

        "EventCode": "0x63",

        "EventName": "BUS_LOCK.ALL",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003"

    },
@@ -27,7 +27,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x63",

        "EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x2"
@@ -38,7 +38,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x63",

        "EventName": "BUS_LOCK.CYCLES_SELF_BLOCK",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x1"
@@ -71,7 +71,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x34",

        "EventName": "C0_STALLS.LOAD_DRAM_HIT",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x4"
@@ -82,7 +82,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x34",

        "EventName": "C0_STALLS.LOAD_L2_HIT",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x1"
@@ -93,7 +93,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x34",

        "EventName": "C0_STALLS.LOAD_LLC_HIT",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x2"
@@ -104,7 +104,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0xcb",

        "EventName": "HW_INTERRUPTS.MASKED",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",

        "SampleAfterValue": "200003",
@@ -116,7 +116,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0xcb",

        "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR)  because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important.",

        "SampleAfterValue": "200003",
@@ -128,7 +128,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0xcb",

        "EventName": "HW_INTERRUPTS.RECEIVED",

        "PDIR_COUNTER": "na",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "203",

        "UMask": "0x1"