Commit b41caade authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'hns3-fixes' 



Hao Lan says:

====================
net: hns3: fix some bug for hns3

There are some bugfixes for the HNS3 ethernet driver. patch#1 fix miss
checking for rx packet. patch#2 fixes VF promisc mode not update
when mac table full bug, and patch#3 fixes a nterrupts not
initialization in VF FLR bug.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 843eb679 6b45d5ff

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

+21 −4
Original line number Diff line number Diff line
@@ -331,9 +331,25 @@ static int hclge_comm_cmd_csq_done(struct hclge_comm_hw *hw) 
	return head == hw->cmq.csq.next_to_use;

}



static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw,

static u32 hclge_get_cmdq_tx_timeout(u16 opcode, u32 tx_timeout)

{

	static const struct hclge_cmdq_tx_timeout_map cmdq_tx_timeout_map[] = {

		{HCLGE_OPC_CFG_RST_TRIGGER, HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS},

	};

	u32 i;



	for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout_map); i++)

		if (cmdq_tx_timeout_map[i].opcode == opcode)

			return cmdq_tx_timeout_map[i].tx_timeout;



	return tx_timeout;

}



static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw, u16 opcode,

				     bool *is_completed)

{

	u32 cmdq_tx_timeout = hclge_get_cmdq_tx_timeout(opcode,

							hw->cmq.tx_timeout);

	u32 timeout = 0;



	do {
@@ -343,7 +359,7 @@ static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw, 
		}

		udelay(1);

		timeout++;

	} while (timeout < hw->cmq.tx_timeout);

	} while (timeout < cmdq_tx_timeout);

}



static int hclge_comm_cmd_convert_err_code(u16 desc_ret)
@@ -407,7 +423,8 @@ static int hclge_comm_cmd_check_result(struct hclge_comm_hw *hw, 
	 * if multi descriptors to be sent, use the first one to check

	 */

	if (HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag)))

		hclge_comm_wait_for_resp(hw, &is_completed);

		hclge_comm_wait_for_resp(hw, le16_to_cpu(desc->opcode),

					 &is_completed);



	if (!is_completed)

		ret = -EBADE;
@@ -529,7 +546,7 @@ int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw) 
	cmdq->crq.desc_num = HCLGE_COMM_NIC_CMQ_DESC_NUM;



	/* Setup Tx write back timeout */

	cmdq->tx_timeout = HCLGE_COMM_CMDQ_TX_TIMEOUT;

	cmdq->tx_timeout = HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT;



	/* Setup queue rings */

	ret = hclge_comm_alloc_cmd_queue(hw, HCLGE_COMM_TYPE_CSQ);

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

+7 −1
Original line number Diff line number Diff line
@@ -54,7 +54,8 @@ 
#define HCLGE_COMM_NIC_SW_RST_RDY		BIT(HCLGE_COMM_NIC_SW_RST_RDY_B)

#define HCLGE_COMM_NIC_CMQ_DESC_NUM_S		3

#define HCLGE_COMM_NIC_CMQ_DESC_NUM		1024

#define HCLGE_COMM_CMDQ_TX_TIMEOUT		30000

#define HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT	30000

#define HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS	500000



enum hclge_opcode_type {

	/* Generic commands */
@@ -360,6 +361,11 @@ struct hclge_comm_caps_bit_map { 
	u16 local_bit;

};



struct hclge_cmdq_tx_timeout_map {

	u32 opcode;

	u32 tx_timeout;

};



struct hclge_comm_firmware_compat_cmd {

	__le32 compat;

	u8 rsv[20];

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -130,7 +130,7 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = { 
		.name = "tx_bd_queue",

		.cmd = HNAE3_DBG_CMD_TX_BD,

		.dentry = HNS3_DBG_DENTRY_TX_BD,

		.buf_len = HNS3_DBG_READ_LEN_4MB,

		.buf_len = HNS3_DBG_READ_LEN_5MB,

		.init = hns3_dbg_bd_file_init,

	},

	{

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#define HNS3_DBG_READ_LEN_128KB	0x20000

#define HNS3_DBG_READ_LEN_1MB	0x100000

#define HNS3_DBG_READ_LEN_4MB	0x400000

#define HNS3_DBG_READ_LEN_5MB	0x500000

#define HNS3_DBG_WRITE_LEN	1024



#define HNS3_DBG_DATA_STR_LEN	32

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+9 −6
Original line number Diff line number Diff line
@@ -8053,13 +8053,16 @@ static void hclge_ae_stop(struct hnae3_handle *handle) 
	/* If it is not PF reset or FLR, the firmware will disable the MAC,

	 * so it only need to stop phy here.

	 */

	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&

	    hdev->reset_type != HNAE3_FUNC_RESET &&

	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {

		hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE,

				       HCLGE_PFC_DISABLE);

		if (hdev->reset_type != HNAE3_FUNC_RESET &&

		    hdev->reset_type != HNAE3_FLR_RESET) {

			hclge_mac_stop_phy(hdev);

			hclge_update_link_status(hdev);

			return;

		}

	}



	hclge_reset_tqp(handle);