dt-bindings: clock: samsung: remove define with number of clocks

#define CLK_SCLK_UART2			248

#define CLK_SCLK_MMC2			249

/*

 * Total number of clocks of main CMU.

 * NOTE: Must be equal to last clock ID increased by one.

 */

#define CLK_NR_CLKS			250

/*

 * CMU DMC

 */

#define CLK_DIV_DMCP			19

#define CLK_DIV_DMCD			20

/*

 * Total number of clocks of main CMU.

 * NOTE: Must be equal to last clock ID increased by one.

 */

#define NR_CLKS_DMC			21

/*

 * CMU ISP

 */

#define CLK_ASYNCAXIM			46

#define CLK_SCLK_MPWM_ISP		47

/*

 * Total number of clocks of CMU_ISP.

 * NOTE: Must be equal to last clock ID increased by one.

 */

#define NR_CLKS_ISP			48

#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */

#define CLK_DIV_GDR		460

#define CLK_DIV_CORE2		461

/* must be greater than maximal clock id */

#define CLK_NR_CLKS		462

/* Exynos4x12 ISP clocks */

#define CLK_ISP_FIMC_ISP		 1

#define CLK_ISP_FIMC_DRC		 2

#define CLK_ISP_DIV_MCUISP0		29

#define CLK_ISP_DIV_MCUISP1		30

#define CLK_NR_ISP_CLKS			31

#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */

#define CLK_MOUT_MPLL		1029

#define CLK_MOUT_VPLLSRC	1030

/* must be greater than maximal clock id */

#define CLK_NR_CLKS		1031

#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */

#define PHYCLK_USBHOST20_PHY_CLK48MOHCI			122

#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK		123

#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK			124

#define TOP_NR_CLK					125

/* List Of Clocks For CMU_EGL */

#define EGL_DOUT_ACLK_EGL				9

#define EGL_DOUT_EGL2					10

#define EGL_DOUT_EGL1					11

#define EGL_NR_CLK					12

/* List Of Clocks For CMU_KFC */

#define KFC_DOUT_KFC_ATCLK				8

#define KFC_DOUT_KFC2					9

#define KFC_DOUT_KFC1					10

#define KFC_NR_CLK					11

/* List Of Clocks For CMU_MIF */

#define MIF_CLK_INTMEM					25

#define MIF_SCLK_LPDDR3PHY_WRAP_U1			26

#define MIF_SCLK_LPDDR3PHY_WRAP_U0			27

#define MIF_NR_CLK					28

/* List Of Clocks For CMU_G3D */

#define G3D_DOUT_ACLK_G3D				4

#define G3D_CLK_G3D_HPM					5

#define G3D_CLK_G3D					6

#define G3D_NR_CLK					7

/* List Of Clocks For CMU_AUD */

#define AUD_SCLK_AUD_UART				13

#define AUD_SCLK_PCM					14

#define AUD_SCLK_I2S					15

#define AUD_NR_CLK					16

/* List Of Clocks For CMU_MFC */

#define MFC_CLK_MFC					3

#define MFC_CLK_SMMU2_MFCM1				4

#define MFC_CLK_SMMU2_MFCM0				5

#define MFC_NR_CLK					6

/* List Of Clocks For CMU_GSCL */

#define GSCL_CLK_SMMU3_MSCL1				24

#define GSCL_SCLK_CSIS1_WRAP				25

#define GSCL_SCLK_CSIS0_WRAP				26

#define GSCL_NR_CLK					27

/* List Of Clocks For CMU_FSYS */

#define FSYS_CLK_SMMU_RTIC				16

#define FSYS_PHYCLK_USBDRD30				17

#define FSYS_PHYCLK_USBHOST20				18

#define FSYS_NR_CLK					19

/* List Of Clocks For CMU_PERI */

#define PERI_SCLK_SPDIF					64

#define PERI_SCLK_I2S					65

#define PERI_SCLK_PCM1					66

#define PERI_NR_CLK					67

/* List Of Clocks For CMU_DISP */

#define DISP_CLK_DP					33

#define DISP_SCLK_PIXEL					34

#define DISP_MOUT_HDMI_PHY_PIXEL_USER			35

#define DISP_NR_CLK					36

/* List Of Clocks For CMU_G2D */

#define G2D_CLK_SMMU_SSS				10

#define G2D_CLK_SMMU_MDMA				11

#define G2D_CLK_SMMU3_G2D				12

#define G2D_NR_CLK					13

/* List Of Clocks For CMU_ISP */

#define ISP_SCLK_SPI0_EXT				31

#define ISP_SCLK_SPI1_EXT				32

#define ISP_SCLK_UART_EXT				33

#define ISP_NR_CLK					34

#endif

#define CLK_USBD301		367

#define CLK_SSS			471

#define CLK_NR_CLKS		512

#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */