Commit b3f89435 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: r9a07g044: Add ADC node 



Add ADC node to R9A07G044 (RZ/G2L) SoC DTSI.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210804202118.25745-4-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent a8675b2d

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

+42 −0
Original line number Diff line number Diff line
@@ -169,6 +169,48 @@ 
			status = "disabled";

		};



		adc: adc@10059000 {

			compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";

			reg = <0 0x10059000 0 0x400>;

			interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;

			clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,

				 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;

			clock-names = "adclk", "pclk";

			resets = <&cpg R9A07G044_ADC_PRESETN>,

				 <&cpg R9A07G044_ADC_ADRST_N>;

			reset-names = "presetn", "adrst-n";

			power-domains = <&cpg>;

			status = "disabled";



			#address-cells = <1>;

			#size-cells = <0>;



			channel@0 {

				reg = <0>;

			};

			channel@1 {

				reg = <1>;

			};

			channel@2 {

				reg = <2>;

			};

			channel@3 {

				reg = <3>;

			};

			channel@4 {

				reg = <4>;

			};

			channel@5 {

				reg = <5>;

			};

			channel@6 {

				reg = <6>;

			};

			channel@7 {

				reg = <7>;

			};

		};



		cpg: clock-controller@11010000 {

			compatible = "renesas,r9a07g044-cpg";

			reg = <0 0x11010000 0 0x10000>;