Commit b3ba797e authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/a6xx: Add some missing header definitions 



Add a definition of the GMU_AHB_FENCE_STATUS_CLR reg and CP_PROTECT_CNTL
bitfields.

This may be substituted with a mesa header sync.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543330/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 3bf84665

drivers/gpu/drm/msm/adreno/a6xx.xml.h

+3 −0
Original line number Diff line number Diff line
@@ -1166,6 +1166,9 @@ static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) 
#define REG_A6XX_CP_DBG_ECO_CNTL				0x00000843



#define REG_A6XX_CP_PROTECT_CNTL				0x0000084f

#define A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE		0x00000008

#define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN		0x00000002

#define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN			0x00000001



static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }

drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h

+2 −0
Original line number Diff line number Diff line
@@ -425,6 +425,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) 


#define REG_A6XX_GMU_AHB_FENCE_STATUS				0x00009313



#define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR			0x00009314



#define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS			0x00009315



#define REG_A6XX_GMU_AO_SPARE_CNTL				0x00009316