Commit b39cb105 authored by Dan Williams's avatar Dan Williams
Browse files

cxl/mem: Register CXL memX devices 



Create the /sys/bus/cxl hierarchy to enumerate:

* Memory Devices (per-endpoint control devices)

* Memory Address Space Devices (platform address ranges with
  interleaving, performance, and persistence attributes)

* Memory Regions (active provisioned memory from an address space device
  that is in use as System RAM or delegated to libnvdimm as Persistent
  Memory regions).

For now, only the per-endpoint control devices are registered on the
'cxl' bus. However, going forward it will provide a mechanism to
coordinate cross-device interleave.

Signed-off-by: default avatarBen Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> (v2)
Link: https://lore.kernel.org/r/20210217040958.1354670-4-ben.widawsky@intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 8adaf747

Documentation/ABI/testing/sysfs-bus-cxl

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+26 −0
Original line number Diff line number Diff line 
What:		/sys/bus/cxl/devices/memX/firmware_version

Date:		December, 2020

KernelVersion:	v5.12

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) "FW Revision" string as reported by the Identify

		Memory Device Output Payload in the CXL-2.0

		specification.



What:		/sys/bus/cxl/devices/memX/ram/size

Date:		December, 2020

KernelVersion:	v5.12

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) "Volatile Only Capacity" as bytes. Represents the

		identically named field in the Identify Memory Device Output

		Payload in the CXL-2.0 specification.



What:		/sys/bus/cxl/devices/memX/pmem/size

Date:		December, 2020

KernelVersion:	v5.12

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) "Persistent Only Capacity" as bytes. Represents the

		identically named field in the Identify Memory Device Output

		Payload in the CXL-2.0 specification.

Documentation/driver-api/cxl/memory-devices.rst

+5 −0
Original line number Diff line number Diff line
@@ -27,3 +27,8 @@ CXL Memory Device 


.. kernel-doc:: drivers/cxl/mem.c

   :internal:



CXL Bus

-------

.. kernel-doc:: drivers/cxl/bus.c

   :doc: cxl bus

drivers/cxl/Makefile

+3 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_CXL_BUS) += cxl_bus.o

obj-$(CONFIG_CXL_MEM) += cxl_mem.o



ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL

cxl_bus-y := bus.o

cxl_mem-y := mem.o

drivers/cxl/bus.c

0 → 100644
+29 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright(c) 2020 Intel Corporation. All rights reserved. */

#include <linux/device.h>

#include <linux/module.h>



/**

 * DOC: cxl bus

 *

 * The CXL bus provides namespace for control devices and a rendezvous

 * point for cross-device interleave coordination.

 */

struct bus_type cxl_bus_type = {

	.name = "cxl",

};

EXPORT_SYMBOL_GPL(cxl_bus_type);



static __init int cxl_bus_init(void)

{

	return bus_register(&cxl_bus_type);

}



static void cxl_bus_exit(void)

{

	bus_unregister(&cxl_bus_type);

}



module_init(cxl_bus_init);

module_exit(cxl_bus_exit);

MODULE_LICENSE("GPL v2");

drivers/cxl/cxl.h

+3 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ 
	(FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) !=                       \

	 CXLMDEV_RESET_NEEDED_NOT)



struct cxl_memdev;

/**

 * struct cxl_mem - A CXL memory device

 * @pdev: The PCI device associated with this CXL device.
@@ -74,6 +75,7 @@ 
struct cxl_mem {

	struct pci_dev *pdev;

	void __iomem *regs;

	struct cxl_memdev *cxlmd;



	void __iomem *status_regs;

	void __iomem *mbox_regs;
@@ -87,4 +89,5 @@ struct cxl_mem { 
	struct range ram_range;

};



extern struct bus_type cxl_bus_type;

#endif /* __CXL_H__ */