Commit b399c13f authored by Adrien Grassein's avatar Adrien Grassein Committed by Shawn Guo
Browse files

arm64: dts: imx8mm-nitrogen-r2: add PWMs 



Add description for the four PWMs.

Signed-off-by: default avatarAdrien Grassein <adrien.grassein@gmail.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 2b6e7da2

arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts

+51 −0
Original line number Diff line number Diff line
@@ -198,6 +198,33 @@ 
	};

};



&pwm1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pwm1>;

	status = "okay";

};



&pwm2 {

	assigned-clocks = <&clk IMX8MM_CLK_PWM2>;

	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;

	assigned-clock-rates = <40000000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pwm2>;

	status = "okay";

};



&pwm3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pwm3>;

	status = "okay";

};



&pwm4 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pwm4>;

	status = "okay";

};



/* BT */

&uart1 {

	pinctrl-names = "default";
@@ -354,6 +381,30 @@ 
		>;

	};



	pinctrl_pwm1: pwm1grp {

		fsl,pins = <

			MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16

		>;

	};



	pinctrl_pwm2: pwm2grp {

		fsl,pins = <

			MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x16

		>;

	};



	pinctrl_pwm3: pwm3grp {

		fsl,pins = <

			MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x16

		>;

	};



	pinctrl_pwm4: pwm4grp {

		fsl,pins = <

			MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16

		>;

	};



	pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {

		fsl,pins = <

			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16