Unverified Commit b36cecf2 authored by Mark Brown's avatar Mark Brown
Browse files

Add Quad SPI driver for StarFive JH7110 SoC 

Merge series from William Qiu <william.qiu@starfivetech.com>:

This patchset adds initial rudimentary support for the StarFive
Quad SPI controller driver. And this driver will be used in
StarFive's VisionFive 2 board.The first patch constrain
minItems/maxItems of resets for JH7110 QSPI and Patch 2 adds
support for StarFive JH7110 QSPI.
parents 1ef5decf 47fef94a

Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml

+33 −4
Original line number Diff line number Diff line
@@ -19,6 +19,33 @@ allOf: 
    then:

      required:

        - power-domains

  - if:

      properties:

        compatible:

          contains:

            const: starfive,jh7110-qspi

    then:

      properties:

        resets:

          minItems: 2

          maxItems: 3



        reset-names:

          minItems: 2

          maxItems: 3

          items:

            enum: [ qspi, qspi-ocp, rstc_ref ]



    else:

      properties:

        resets:

          maxItems: 2



        reset-names:

          minItems: 1

          maxItems: 2

          items:

            enum: [ qspi, qspi-ocp ]



properties:

  compatible:
@@ -30,6 +57,7 @@ properties: 
              - intel,lgm-qspi

              - xlnx,versal-ospi-1.0

              - intel,socfpga-qspi

              - starfive,jh7110-qspi

          - const: cdns,qspi-nor

      - const: cdns,qspi-nor
@@ -79,13 +107,14 @@ properties: 
    maxItems: 1



  resets:

    maxItems: 2

    minItems: 2

    maxItems: 3



  reset-names:

    minItems: 1

    maxItems: 2

    minItems: 2

    maxItems: 3

    items:

      enum: [ qspi, qspi-ocp ]

      enum: [ qspi, qspi-ocp, rstc_ref ]



required:

  - compatible

drivers/spi/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -239,7 +239,7 @@ config SPI_CADENCE 


config SPI_CADENCE_QUADSPI

	tristate "Cadence Quad SPI controller"

	depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)

	depends on OF && (ARM || ARM64 || X86 || RISCV || COMPILE_TEST)

	help

	  Enable support for the Cadence Quad SPI Flash controller.

drivers/spi/spi-cadence-quadspi.c

+20 −1
Original line number Diff line number Diff line
@@ -1615,7 +1615,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) 
static int cqspi_probe(struct platform_device *pdev)

{

	const struct cqspi_driver_platdata *ddata;

	struct reset_control *rstc, *rstc_ocp;

	struct reset_control *rstc, *rstc_ocp, *rstc_ref;

	struct device *dev = &pdev->dev;

	struct spi_master *master;

	struct resource *res_ahb;
@@ -1705,6 +1705,17 @@ static int cqspi_probe(struct platform_device *pdev) 
		goto probe_reset_failed;

	}



	if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {

		rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");

		if (IS_ERR(rstc_ref)) {

			ret = PTR_ERR(rstc_ref);

			dev_err(dev, "Cannot get QSPI REF reset.\n");

			goto probe_reset_failed;

		}

		reset_control_assert(rstc_ref);

		reset_control_deassert(rstc_ref);

	}



	reset_control_assert(rstc);

	reset_control_deassert(rstc);
@@ -1859,6 +1870,10 @@ static const struct cqspi_driver_platdata versal_ospi = { 
	.get_dma_status = cqspi_get_versal_dma_status,

};



static const struct cqspi_driver_platdata jh7110_qspi = {

	.quirks = CQSPI_DISABLE_DAC_MODE,

};



static const struct of_device_id cqspi_dt_ids[] = {

	{

		.compatible = "cdns,qspi-nor",
@@ -1884,6 +1899,10 @@ static const struct of_device_id cqspi_dt_ids[] = { 
		.compatible = "intel,socfpga-qspi",

		.data = &socfpga_qspi,

	},

	{

		.compatible = "starfive,jh7110-qspi",

		.data = &jh7110_qspi,

	},

	{ /* end of table */ }

};