Commit b33139ee authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: add helper to init rlc fw in header v2_4 



To initialize rlc firmware in header v2_4

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c1c3f41f

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c

+60 −0
Original line number Diff line number Diff line
@@ -441,3 +441,63 @@ static void amdgpu_gfx_rlc_init_microcode_v2_3(struct amdgpu_device *adev) 
		}

	}

}



static void amdgpu_gfx_rlc_init_microcode_v2_4(struct amdgpu_device *adev)

{

	const struct rlc_firmware_header_v2_4 *rlc_hdr;

	struct amdgpu_firmware_info *info;



	rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data;

	adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_size_bytes);

	adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes);

	adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_bytes);

	adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes);

	adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_bytes);

	adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes);

	adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_bytes);

	adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes);

	adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_bytes);

	adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes);



	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}

	}

}