Commit b31587fe authored by Bartosz Wawrzyniak's avatar Bartosz Wawrzyniak Committed by David S. Miller
Browse files

net: macb: Set MDIO clock divisor for pclk higher than 160MHz 



Currently macb sets clock divisor for pclk up to 160 MHz.
Function gem_mdc_clk_div was updated to enable divisor
for higher values of pclk.

Signed-off-by: default avatarBartosz Wawrzyniak <bwawrzyn@cisco.com>
Reviewed-by: default avatarMichal Kubiak <michal.kubiak@intel.com>
Acked-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent df28e869

drivers/net/ethernet/cadence/macb.h

+2 −0
Original line number Diff line number Diff line
@@ -692,6 +692,8 @@ 
#define GEM_CLK_DIV48				3

#define GEM_CLK_DIV64				4

#define GEM_CLK_DIV96				5

#define GEM_CLK_DIV128				6

#define GEM_CLK_DIV224				7



/* Constants for MAN register */

#define MACB_MAN_C22_SOF			1

drivers/net/ethernet/cadence/macb_main.c

+5 −1
Original line number Diff line number Diff line
@@ -2640,8 +2640,12 @@ static u32 gem_mdc_clk_div(struct macb *bp) 
		config = GEM_BF(CLK, GEM_CLK_DIV48);

	else if (pclk_hz <= 160000000)

		config = GEM_BF(CLK, GEM_CLK_DIV64);

	else

	else if (pclk_hz <= 240000000)

		config = GEM_BF(CLK, GEM_CLK_DIV96);

	else if (pclk_hz <= 320000000)

		config = GEM_BF(CLK, GEM_CLK_DIV128);

	else

		config = GEM_BF(CLK, GEM_CLK_DIV224);



	return config;

}