Commit b31578f6 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Marc Zyngier
Browse files

arm64/mm: Define ID_AA64MMFR0_TGRAN_2_SHIFT 



Streamline the Stage-2 TGRAN value extraction from ID_AA64MMFR0 register by
adding a page size agnostic ID_AA64MMFR0_TGRAN_2_SHIFT. This is similar to
the existing Stage-1 TGRAN shift i.e ID_AA64MMFR0_TGRAN_SHIFT.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Acked-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1628569782-30213-1-git-send-email-anshuman.khandual@arm.com
parent 6fadc124

arch/arm64/include/asm/sysreg.h

+3 −0
Original line number Diff line number Diff line
@@ -1028,14 +1028,17 @@ 


#if defined(CONFIG_ARM64_4K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN4_SHIFT

#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN4_2_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN4_SUPPORTED

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	0x7

#elif defined(CONFIG_ARM64_16K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN16_SHIFT

#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN16_2_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN16_SUPPORTED

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	0xF

#elif defined(CONFIG_ARM64_64K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN64_SHIFT

#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN64_2_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN64_SUPPORTED

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	0x7

#endif

arch/arm64/kvm/reset.c

+2 −15
Original line number Diff line number Diff line
@@ -311,7 +311,7 @@ u32 get_kvm_ipa_limit(void) 


int kvm_set_ipa_limit(void)

{

	unsigned int parange, tgran_2;

	unsigned int parange;

	u64 mmfr0;



	mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
@@ -322,20 +322,7 @@ int kvm_set_ipa_limit(void) 
	 * Check with ARMv8.5-GTG that our PAGE_SIZE is supported at

	 * Stage-2. If not, things will stop very quickly.

	 */

	switch (PAGE_SIZE) {

	default:

	case SZ_4K:

		tgran_2 = ID_AA64MMFR0_TGRAN4_2_SHIFT;

		break;

	case SZ_16K:

		tgran_2 = ID_AA64MMFR0_TGRAN16_2_SHIFT;

		break;

	case SZ_64K:

		tgran_2 = ID_AA64MMFR0_TGRAN64_2_SHIFT;

		break;

	}



	switch (cpuid_feature_extract_unsigned_field(mmfr0, tgran_2)) {

	switch (cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_TGRAN_2_SHIFT)) {

	case ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE:

		kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");

		return -EINVAL;