Commit b2ef0661 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Relocate intel_dp_program_link_training_pattern() 



intel_dp_program_link_training_pattern() clearly belongs in
intel_dp_link_training.c. Make it so.

Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210318161015.22070-4-ville.syrjala@linux.intel.com
parent 6721af21

drivers/gpu/drm/i915/display/intel_dp.c

+0 −33
Original line number Diff line number Diff line
@@ -3386,39 +3386,6 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, 
	intel_de_posting_read(dev_priv, intel_dp->output_reg);

}



static char dp_training_pattern_name(u8 train_pat)

{

	switch (train_pat) {

	case DP_TRAINING_PATTERN_1:

	case DP_TRAINING_PATTERN_2:

	case DP_TRAINING_PATTERN_3:

		return '0' + train_pat;

	case DP_TRAINING_PATTERN_4:

		return '4';

	default:

		MISSING_CASE(train_pat);

		return '?';

	}

}



void

intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,

				       const struct intel_crtc_state *crtc_state,

				       u8 dp_train_pat)

{

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);



	if (train_pat != DP_TRAINING_PATTERN_DISABLE)

		drm_dbg_kms(&dev_priv->drm,

			    "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",

			    encoder->base.base.id, encoder->base.name,

			    dp_training_pattern_name(train_pat));



	intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);

}



static void

intel_dp_link_down(struct intel_encoder *encoder,

		   const struct intel_crtc_state *old_crtc_state)

drivers/gpu/drm/i915/display/intel_dp.h

+0 −4
Original line number Diff line number Diff line
@@ -87,10 +87,6 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, 
void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,

			  unsigned int frontbuffer_bits);



void

intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,

				       const struct intel_crtc_state *crtc_state,

				       u8 dp_train_pat);

void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,

			   u8 *link_bw, u8 *rate_select);

bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

+33 −0
Original line number Diff line number Diff line
@@ -367,6 +367,39 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, 
	return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;

}



static char dp_training_pattern_name(u8 train_pat)

{

	switch (train_pat) {

	case DP_TRAINING_PATTERN_1:

	case DP_TRAINING_PATTERN_2:

	case DP_TRAINING_PATTERN_3:

		return '0' + train_pat;

	case DP_TRAINING_PATTERN_4:

		return '4';

	default:

		MISSING_CASE(train_pat);

		return '?';

	}

}



void

intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,

				       const struct intel_crtc_state *crtc_state,

				       u8 dp_train_pat)

{

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);



	if (train_pat != DP_TRAINING_PATTERN_DISABLE)

		drm_dbg_kms(&dev_priv->drm,

			    "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",

			    encoder->base.base.id, encoder->base.name,

			    dp_training_pattern_name(train_pat));



	intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);

}



void intel_dp_set_signal_levels(struct intel_dp *intel_dp,

				const struct intel_crtc_state *crtc_state,

				enum drm_dp_phy dp_phy)

drivers/gpu/drm/i915/display/intel_dp_link_training.h

+3 −0
Original line number Diff line number Diff line
@@ -17,6 +17,9 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp, 
			       const struct intel_crtc_state *crtc_state,

			       enum drm_dp_phy dp_phy,

			       const u8 link_status[DP_LINK_STATUS_SIZE]);

void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,

					    const struct intel_crtc_state *crtc_state,

					    u8 dp_train_pat);

void intel_dp_set_signal_levels(struct intel_dp *intel_dp,

				const struct intel_crtc_state *crtc_state,

				enum drm_dp_phy dp_phy);