dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT8365 Pin Controller

maintainers:

  - Zhiyong Tao <zhiyong.tao@mediatek.com>

  - Bernhard Rosenkränzer <bero@baylibre.com>

description: |

  The MediaTek's MT8365 Pin controller is used to control SoC pins.

properties:

  compatible:

    const: mediatek,mt8365-pinctrl

  reg:

    maxItems: 1

  mediatek,pctl-regmap:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      maxItems: 1

    minItems: 1

    maxItems: 2

    description: |

      Should be phandles of the syscfg node.

  gpio-controller: true

  "#gpio-cells":

    const: 2

    description: |

      Number of cells in GPIO specifier. Since the generic GPIO

      binding is used, the amount of cells must be specified as 2. See the below

      mentioned gpio binding representation for description of particular cells.

  interrupt-controller: true

  interrupts:

    maxItems: 1

  "#interrupt-cells":

    const: 2

patternProperties:

  "-pins$":

    type: object

    additionalProperties: false

    patternProperties:

      "pins$":

        type: object

        additionalProperties: false

        description: |

          A pinctrl node should contain at least one subnode representing the

          pinctrl groups available on the machine. Each subnode will list the

          pins it needs, and how they should be configured, with regard to muxer

          configuration, pullups, drive strength, input enable/disable and input

          schmitt.

        $ref: /schemas/pinctrl/pincfg-node.yaml

        properties:

          pinmux:

            description:

              integer array, represents gpio pin number and mux setting.

              Supported pin number and mux varies for different SoCs, and are

              defined as macros in <soc>-pinfunc.h directly.

          bias-disable: true

          bias-pull-up:

            description: |

              Besides generic pinconfig options, it can be used as the pull up

              settings for 2 pull resistors, R0 and R1. User can configure those

              special pins.

          bias-pull-down: true

          input-enable: true

          input-disable: true

          output-low: true

          output-high: true

          input-schmitt-enable: true

          input-schmitt-disable: true

          mediatek,drive-strength-adv:

            description: |

              Describe the specific driving setup property.

              For I2C pins, the existing generic driving setup can only support

              2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they

              can support 0.125/0.25/0.5/1mA adjustment. If we enable specific

              driving setup, the existing generic setup will be disabled.

              The specific driving setup is controlled by E1E0EN.

              When E1=0/E0=0, the strength is 0.125mA.

              When E1=0/E0=1, the strength is 0.25mA.

              When E1=1/E0=0, the strength is 0.5mA.

              When E1=1/E0=1, the strength is 1mA.

              EN is used to enable or disable the specific driving setup.

              Valid arguments are described as below:

              0: (E1, E0, EN) = (0, 0, 0)

              1: (E1, E0, EN) = (0, 0, 1)

              2: (E1, E0, EN) = (0, 1, 0)

              3: (E1, E0, EN) = (0, 1, 1)

              4: (E1, E0, EN) = (1, 0, 0)

              5: (E1, E0, EN) = (1, 0, 1)

              6: (E1, E0, EN) = (1, 1, 0)

              7: (E1, E0, EN) = (1, 1, 1)

              So the valid arguments are from 0 to 7.

            $ref: /schemas/types.yaml#/definitions/uint32

            enum: [0, 1, 2, 3, 4, 5, 6, 7]

          mediatek,pull-up-adv:

            description: |

              Pull up setings for 2 pull resistors, R0 and R1. User can

              configure those special pins. Valid arguments are described as below:

              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.

              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.

            $ref: /schemas/types.yaml#/definitions/uint32

            enum: [0, 1, 2, 3]

          mediatek,pull-down-adv:

            description: |

              Pull down settings for 2 pull resistors, R0 and R1. User can

              configure those special pins. Valid arguments are described as below:

              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.

              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.

            $ref: /schemas/types.yaml#/definitions/uint32

            enum: [0, 1, 2, 3]

          mediatek,tdsel:

            description: |

              An integer describing the steps for output level shifter duty

              cycle when asserted (high pulse width adjustment). Valid arguments

              are from 0 to 15.

            $ref: /schemas/types.yaml#/definitions/uint32

          mediatek,rdsel:

            description: |

              An integer describing the steps for input level shifter duty cycle

              when asserted (high pulse width adjustment). Valid arguments are

              from 0 to 63.

            $ref: /schemas/types.yaml#/definitions/uint32

        required:

          - pinmux

required:

  - compatible

  - reg

  - gpio-controller

  - "#gpio-cells"

allOf:

  - $ref: pinctrl.yaml#

additionalProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/pinctrl/mt8365-pinfunc.h>

    soc {

      #address-cells = <2>;

      #size-cells = <2>;

      pio: pinctrl@1000b000 {

        compatible = "mediatek,mt8365-pinctrl";

        reg = <0 0x1000b000 0 0x1000>;

        mediatek,pctl-regmap = <&syscfg_pctl>;

        gpio-controller;

        #gpio-cells = <2>;

        interrupt-controller;

        #interrupt-cells = <2>;

        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;

        pio-pins {

          pins {

            pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>, <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;

            mediatek,pull-up-adv = <3>;

            mediatek,drive-strength-adv = <00>;

            bias-pull-up;

          };

        };

      };

    };