Commit b2c2c21a authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-riscv-fixes-5.18-1' of https://github.com/kvm-riscv/linux into HEAD 

KVM/riscv fixes for 5.18, take #1

- Remove hgatp zeroing in kvm_arch_vcpu_put()

- Fix alignment of the guest_hang() in KVM selftest

- Fix PTE A and D bits in KVM selftest

- Missing #include in vcpu_fp.c
parents a44e2c20 4054eee9

arch/riscv/kvm/vcpu.c

+0 −2
Original line number Diff line number Diff line
@@ -653,8 +653,6 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 
				     vcpu->arch.isa);

	kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context);



	csr_write(CSR_HGATP, 0);



	csr->vsstatus = csr_read(CSR_VSSTATUS);

	csr->vsie = csr_read(CSR_VSIE);

	csr->vstvec = csr_read(CSR_VSTVEC);

arch/riscv/kvm/vcpu_fp.c

+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/err.h>

#include <linux/kvm_host.h>

#include <linux/uaccess.h>

#include <asm/hwcap.h>



#ifdef CONFIG_FPU

void kvm_riscv_vcpu_fp_reset(struct kvm_vcpu *vcpu)

tools/testing/selftests/kvm/include/riscv/processor.h

+3 −1
Original line number Diff line number Diff line
@@ -101,7 +101,9 @@ static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id, 
#define PGTBL_PTE_WRITE_SHIFT			2

#define PGTBL_PTE_READ_MASK			0x0000000000000002ULL

#define PGTBL_PTE_READ_SHIFT			1

#define PGTBL_PTE_PERM_MASK			(PGTBL_PTE_EXECUTE_MASK | \

#define PGTBL_PTE_PERM_MASK			(PGTBL_PTE_ACCESSED_MASK | \

						 PGTBL_PTE_DIRTY_MASK | \

						 PGTBL_PTE_EXECUTE_MASK | \

						 PGTBL_PTE_WRITE_MASK | \

						 PGTBL_PTE_READ_MASK)

#define PGTBL_PTE_VALID_MASK			0x0000000000000001ULL

tools/testing/selftests/kvm/lib/riscv/processor.c

+1 −1
Original line number Diff line number Diff line
@@ -268,7 +268,7 @@ void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint8_t indent) 
		core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6);

}



static void guest_hang(void)

static void __aligned(16) guest_hang(void)

{

	while (1)

		;