Commit b289cdec authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 



As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be
1600 MHz, but with current multiplier and divider values this resulted
to 1596 MHz.

This patch updates the multiplier and divider values for PLL2 and PLL3
so that we get the exact (1600 MHz) values.

Fixes: 17f0ff3d ("clk: renesas: Add support for R9A07G044 SoC")
Suggested-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211223093223.4725-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent d843e61e

drivers/clk/renesas/r9a07g044-cpg.c

+2 −2
Original line number Diff line number Diff line
@@ -88,8 +88,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),

	DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),

	DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),

	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),

	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),

	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),

	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),

	DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),

	DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),