Commit b24dcf1d authored by Chris Wilson's avatar Chris Wilson Committed by Rodrigo Vivi
Browse files

drm/i915/gt: Serialize GRDOM access between multiple engine resets 



Don't allow two engines to be reset in parallel, as they would both
try to select a reset bit (and send requests to common registers)
and wait on that register, at the same time. Serialize control of
the reset requests/acks using the uncore->lock, which will also ensure
that no other GT state changes at the same time as the actual reset.

Cc: stable@vger.kernel.org # v4.4 and upper
Reported-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@intel.com>
Reviewed-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Acked-by: default avatarThomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@kernel.org>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e0a2d894e77aed7c2e36b0d1abdc7dbac3011729.1657639152.git.mchehab@kernel.org


(cherry picked from commit 336561a9)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent aff1e0b0

drivers/gpu/drm/i915/gt/intel_reset.c

+28 −9
Original line number Diff line number Diff line
@@ -300,7 +300,7 @@ static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask) 
	return err;

}



static int gen6_reset_engines(struct intel_gt *gt,

static int __gen6_reset_engines(struct intel_gt *gt,

				intel_engine_mask_t engine_mask,

				unsigned int retry)

{
@@ -321,6 +321,20 @@ static int gen6_reset_engines(struct intel_gt *gt, 
	return gen6_hw_domain_reset(gt, hw_mask);

}



static int gen6_reset_engines(struct intel_gt *gt,

			      intel_engine_mask_t engine_mask,

			      unsigned int retry)

{

	unsigned long flags;

	int ret;



	spin_lock_irqsave(&gt->uncore->lock, flags);

	ret = __gen6_reset_engines(gt, engine_mask, retry);

	spin_unlock_irqrestore(&gt->uncore->lock, flags);



	return ret;

}



static struct intel_engine_cs *find_sfc_paired_vecs_engine(struct intel_engine_cs *engine)

{

	int vecs_id;
@@ -487,7 +501,7 @@ static void gen11_unlock_sfc(struct intel_engine_cs *engine) 
	rmw_clear_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit);

}



static int gen11_reset_engines(struct intel_gt *gt,

static int __gen11_reset_engines(struct intel_gt *gt,

				 intel_engine_mask_t engine_mask,

				 unsigned int retry)

{
@@ -583,8 +597,11 @@ static int gen8_reset_engines(struct intel_gt *gt, 
	struct intel_engine_cs *engine;

	const bool reset_non_ready = retry >= 1;

	intel_engine_mask_t tmp;

	unsigned long flags;

	int ret;



	spin_lock_irqsave(&gt->uncore->lock, flags);



	for_each_engine_masked(engine, gt, engine_mask, tmp) {

		ret = gen8_engine_reset_prepare(engine);

		if (ret && !reset_non_ready)
@@ -612,17 +629,19 @@ static int gen8_reset_engines(struct intel_gt *gt, 
	 * This is best effort, so ignore any error from the initial reset.

	 */

	if (IS_DG2(gt->i915) && engine_mask == ALL_ENGINES)

		gen11_reset_engines(gt, gt->info.engine_mask, 0);

		__gen11_reset_engines(gt, gt->info.engine_mask, 0);



	if (GRAPHICS_VER(gt->i915) >= 11)

		ret = gen11_reset_engines(gt, engine_mask, retry);

		ret = __gen11_reset_engines(gt, engine_mask, retry);

	else

		ret = gen6_reset_engines(gt, engine_mask, retry);

		ret = __gen6_reset_engines(gt, engine_mask, retry);



skip_reset:

	for_each_engine_masked(engine, gt, engine_mask, tmp)

		gen8_engine_reset_cancel(engine);



	spin_unlock_irqrestore(&gt->uncore->lock, flags);



	return ret;

}