Commit b21b2454 authored by Yu Zhang's avatar Yu Zhang Committed by JiangShui
Browse files

hns3 udma: support dfx function of query resources 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I85R2F


CVE: NA

---------------------------------------------------------------------

This patch supports dfx function of query resources as follows:
1. query resources by write ID of resources to sysfs node: TP context,
JFC context, JFR context, and SEG entry.
2. query resources by URMA: ID list of each resources, details of TP,
JFS, JFR, JFC, Jetty, and SEG.

Signed-off-by: default avatarYu Zhang <zhangyu709@huawei.com>
parent d90f5613

drivers/ub/hw/hns3/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ $(MODULE_NAME)-objs := hns3_udma_hw.o hns3_udma_main.o hns3_udma_cmd.o \ 
			hns3_udma_hem.o hns3_udma_qp.o hns3_udma_eq.o \

			hns3_udma_db.o hns3_udma_jfc.o hns3_udma_jfr.o \

			hns3_udma_segment.o  hns3_udma_tp.o hns3_udma_jfs.o \

			hns3_udma_jetty.o hns3_udma_sysfs.o hns3_udma_dca.o

			hns3_udma_jetty.o hns3_udma_sysfs.o hns3_udma_dca.o \

			hns3_udma_dfx.o



obj-$(CONFIG_UB_UDMA_HNS3) := hns3_udma.o

drivers/ub/hw/hns3/hns3_udma_device.h

+7 −0
Original line number Diff line number Diff line
@@ -250,6 +250,12 @@ enum udma_qp_state { 
	QPS_ERR = 6,

};



enum udma_eq_dfx {

	UDMA_DFX_AEQE,

	UDMA_DFX_CEQE,

	UDMA_DFX_EQ_TOTAL

};



enum {

	UDMA_BUF_DIRECT = BIT(0),

	UDMA_BUF_NOSLEEP = BIT(1),
@@ -837,6 +843,7 @@ struct udma_dev { 
	struct udma_hem_table		cqc_timer_table;

	struct udma_hem_table		gmv_table;

	uint64_t			dwqe_page;

	uint64_t			dfx_cnt[UDMA_DFX_EQ_TOTAL];

	struct list_head		qp_list;

	spinlock_t			qp_list_lock;

	struct list_head		dip_list;

drivers/ub/hw/hns3/hns3_udma_dfx.c

0 → 100644
+1161 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/ub/hw/hns3/hns3_udma_dfx.h

0 → 100644
+139 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Huawei UDMA Linux driver

 * Copyright (c) 2023-2023 Hisilicon Limited.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

 * for more details.

 *

 */



#ifndef _UDMA_DFX_H

#define _UDMA_DFX_H



#include <linux/fs.h>

#include "hns3_udma_device.h"



#define DFX_DEVICE_NAME "udma_dfx"

#define MAX_UDMA_DEV	16

#define MAX_TP_CNT	256

#define MAX_JFS_CNT	256

#define MAX_JFR_CNT	256

#define MAX_JETTY_CNT	256

#define MAX_JFC_CNT	256

#define MAX_SEG_CNT	256

#define UDMA_DFX_FILE_ATTR_DEF(file_name, func_show, func_store) \

static struct udma_dfx_sys_attr g_sysfs_udma_##file_name##_attr = {\

	{\

		.name = #file_name,\

		.mode = 0644,\

	},\

	.pub_show  = (func_show),\

	.pub_store = (func_store),\

}



#define HW_ATTRS_LIST_MEMBER(file_name) (&g_sysfs_udma_##file_name##_attr.attr)

#define MAX_CHAR_NUM_DEV_NAME	12

#define UDMA_DFX_STR_LEN_MAX 20



struct udma_dfx_info;



struct udma_dfx_sys_attr {

	struct attribute attr;

	int (*pub_show)(struct udma_dfx_info *udma_dfx);

	int (*pub_store)(const char *buf, struct udma_dfx_info *udma_dfx);

};



struct udma_dfx_dev_info {

	char dev_name[MAX_CHAR_NUM_DEV_NAME];

};



struct udma_dfx_ops {

	int (*add_sysfs)(struct udma_dfx_info *info);

	void (*del_sysfs)(struct udma_dfx_info *info);

};



struct tpn_list {

	uint32_t		tpn;

	struct list_head	node;

	spinlock_t		node_lock;

};



struct jfs_list {

	uint32_t		jfs_id;

	uint8_t			state;

	uint16_t		depth;

	uint8_t			pri;

	uint32_t		jfc_id;

	struct list_head	node;

	spinlock_t		node_lock;

};



struct jfr_list {

	uint32_t		jfr_id;

	uint32_t		jfc_id;

	struct list_head	node;

	spinlock_t		node_lock;

};



struct jetty_list {

	uint32_t		jetty_id;

	uint8_t			state;

	uint32_t		jfs_depth;

	uint32_t		jfr_depth;

	uint8_t			pri;

	uint32_t		jfc_s_id;

	uint32_t		jfc_r_id;

	uint32_t		jfr_id;

	struct list_head	node;

	spinlock_t		node_lock;

};



struct jfc_list {

	uint32_t		jfc_id;

	struct list_head	node;

	spinlock_t		node_lock;

};



struct seg_list {

	uint32_t		pd;

	uint64_t		iova;

	uint32_t		len;

	uint32_t		key_id;

	struct list_head	node;

	spinlock_t		node_lock;

};



struct udma_dfx_info {

	struct udma_dfx_dev_info	dev;

	struct udma_dfx_ops		*ops;

	struct device			*drv_dev;

	struct kobject			kobj;

	struct tpn_list			*tpn_list;

	struct jfs_list			*jfs_list;

	struct jfr_list			*jfr_list;

	struct jetty_list		*jetty_list;

	struct jfc_list			*jfc_list;

	struct seg_list			*seg_list;

	void				*priv;

};



struct udma_dfx_dev {

	struct udma_dfx_info	*dfx;

	struct udma_dev		*dev;

};



extern struct udma_dfx_dev g_udma_dfx_list[MAX_UDMA_DEV];



int udma_dfx_init(struct udma_dev *udma_dev);

void udma_dfx_uninit(struct udma_dev *udma_dev);

int udma_find_dfx_dev(struct udma_dev *udma_dev, int *num);

int udma_query_res(const struct ubcore_device *dev, struct ubcore_res_key *key,

		   struct ubcore_res_val *val);



#endif /* _UDMA_DFX_H */

drivers/ub/hw/hns3/hns3_udma_eq.c

+2 −0
Original line number Diff line number Diff line
@@ -339,6 +339,7 @@ static int udma_aeq_int(struct udma_dev *udma_dev, struct udma_eq *eq) 


		++eq->cons_index;



		udma_dev->dfx_cnt[UDMA_DFX_AEQE]++;

		BUILD_BUG_ON(sizeof(struct udma_aeqe) > TRACE_AEQE_LEN_MAX);



		udma_init_irq_work(udma_dev, eq, aeqe, queue_num);
@@ -381,6 +382,7 @@ static int udma_ceq_int(struct udma_dev *udma_dev, 
		udma_jfc_completion(udma_dev, cqn);



		++eq->cons_index;

		udma_dev->dfx_cnt[UDMA_DFX_CEQE]++;

		ceqe_found = 1;



		ceqe = next_ceqe_sw_v2(eq);