Commit b1f80a5a authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915/gt: Document function to decode register state context 



It's not obvious how the encode/decode of the per platform tables is
done. Document it so while adding tables for new platforms people can be
confident they right things is being done.

Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220930050903.3479619-3-lucas.demarchi@intel.com
parent c3d5cfe7

drivers/gpu/drm/i915/gt/intel_lrc.c

+24 −0
Original line number Diff line number Diff line
@@ -20,6 +20,30 @@ 
#include "intel_ring.h"

#include "shmem_utils.h"



/*

 * The per-platform tables are u8-encoded in @data. Decode @data and set the

 * addresses' offset and commands in @regs. The following encoding is used

 * for each byte. There are 2 steps: decoding commands and decoding addresses.

 *

 * Commands:

 * [7]: create NOPs - number of NOPs are set in lower bits

 * [6]: When creating MI_LOAD_REGISTER_IMM command, allow to set

 *      MI_LRI_FORCE_POSTED

 * [5:0]: Number of NOPs or registers to set values to in case of

 *        MI_LOAD_REGISTER_IMM

 *

 * Addresses: these are decoded after a MI_LOAD_REGISTER_IMM command by "count"

 * number of registers. They are set by using the REG/REG16 macros: the former

 * is used for offsets smaller than 0x200 while the latter is for values bigger

 * than that. Those macros already set all the bits documented below correctly:

 *

 * [7]: When a register offset needs more than 6 bits, use additional bytes, to

 *      follow, for the lower bits

 * [6:0]: Register offset, without considering the engine base.

 *

 * This function only tweaks the commands and register offsets. Values are not

 * filled out.

 */

static void set_offsets(u32 *regs,

			const u8 *data,

			const struct intel_engine_cs *engine,