Commit b1c77b51 authored by Wenpeng Liang's avatar Wenpeng Liang Committed by Zheng Zengkai
Browse files

RDMA/hns: Use hr_reg_read() instead of remaining roce_get_xxx() 

mainline inclusion
from mainline-for-linus
commit 813c9802
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5CHIG
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git/commit/?id=813c980294d48362ead5422b056072ed214ca2bf

----------------------------------------------------------------------

To reduce the code size and make the code clearer, replace all
roce_get_xxx() with hr_reg_read() to read the data fields.

Link: https://lore.kernel.org/r/20220512080012.38728-3-liangwenpeng@huawei.com


Signed-off-by: default avatarWenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Signed-off-by: default avatarZhengfeng Luo <luozhengfeng@h-partners.com>
Reviewed-by: default avatarYangyang Li <liyangyang20@huawei.com>
Reviewed-by: default avatarYue Haibing <yuehaibing@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 0e5a7b2f

drivers/infiniband/hw/hns/hns_roce_device.h

+12 −2
Original line number Diff line number Diff line
@@ -129,8 +129,6 @@ enum hns_roce_event { 
	HNS_ROCE_EVENT_TYPE_INVALID_XRCETH	      = 0x17,

};



#define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12



enum {

	HNS_ROCE_CAP_FLAG_REREG_MR		= BIT(0),

	HNS_ROCE_CAP_FLAG_ROCE_V1_V2		= BIT(1),
@@ -652,6 +650,11 @@ struct hns_roce_ceqe { 
	__le32	rsv[15];

};



#define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l)



#define CEQE_CQN CEQE_FIELD_LOC(23, 0)

#define CEQE_OWNER CEQE_FIELD_LOC(31, 31)



struct hns_roce_aeqe {

	__le32 asyn;

	union {
@@ -671,6 +674,13 @@ struct hns_roce_aeqe { 
	__le32 rsv[12];

};



#define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l)



#define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0)

#define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8)

#define AEQE_OWNER AEQE_FIELD_LOC(31, 31)

#define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32)



struct hns_roce_eq {

	struct hns_roce_dev		*hr_dev;

	void __iomem			*db_reg;

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+38 −99
Original line number Diff line number Diff line
@@ -1483,7 +1483,7 @@ static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 
		if (ret)

			continue;



		if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) {

		if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) {

			if (vf_id == 0)

				hr_dev->is_reset = true;

			return;
@@ -2240,87 +2240,39 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 
	ctx_hop_num		     = resp_b->ctx_hop_num;

	pbl_hop_num		     = resp_b->pbl_hop_num;



	caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds,

					    V2_QUERY_PF_CAPS_C_NUM_PDS_M,

					    V2_QUERY_PF_CAPS_C_NUM_PDS_S);

	caps->flags = roce_get_field(resp_c->cap_flags_num_pds,

				     V2_QUERY_PF_CAPS_C_CAP_FLAGS_M,

				     V2_QUERY_PF_CAPS_C_CAP_FLAGS_S);

	caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS);



	caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS);

	caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<

		       HNS_ROCE_CAP_FLAGS_EX_SHIFT;



	caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs,

					    V2_QUERY_PF_CAPS_C_NUM_CQS_M,

					    V2_QUERY_PF_CAPS_C_NUM_CQS_S);

	caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs,

						V2_QUERY_PF_CAPS_C_MAX_GID_M,

						V2_QUERY_PF_CAPS_C_MAX_GID_S);



	caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth,

					     V2_QUERY_PF_CAPS_C_CQ_DEPTH_M,

					     V2_QUERY_PF_CAPS_C_CQ_DEPTH_S);

	caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws,

					      V2_QUERY_PF_CAPS_C_NUM_MRWS_M,

					      V2_QUERY_PF_CAPS_C_NUM_MRWS_S);

	caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps,

					    V2_QUERY_PF_CAPS_C_NUM_QPS_M,

					    V2_QUERY_PF_CAPS_C_NUM_QPS_S);

	caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps,

						V2_QUERY_PF_CAPS_C_MAX_ORD_M,

						V2_QUERY_PF_CAPS_C_MAX_ORD_S);

	caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS);

	caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID);

	caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH);

	caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS);

	caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS);

	caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD);

	caps->max_qp_dest_rdma = caps->max_qp_init_rdma;

	caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);

	caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs,

					     V2_QUERY_PF_CAPS_D_NUM_SRQS_M,

					     V2_QUERY_PF_CAPS_D_NUM_SRQS_S);

	caps->cong_type = roce_get_field(resp_d->wq_hop_num_max_srqs,

					 V2_QUERY_PF_CAPS_D_CONG_TYPE_M,

					 V2_QUERY_PF_CAPS_D_CONG_TYPE_S);

	caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);



	caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth,

					       V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M,

					       V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S);

	caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth,

						V2_QUERY_PF_CAPS_D_NUM_CEQS_M,

						V2_QUERY_PF_CAPS_D_NUM_CEQS_S);



	caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth,

					       V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M,

					       V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S);

	caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,

					    V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M,

					    V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S);

	caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,

					    V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M,

					    V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S);

	caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds,

					    V2_QUERY_PF_CAPS_D_RSV_PDS_M,

					    V2_QUERY_PF_CAPS_D_RSV_PDS_S);

	caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds,

					     V2_QUERY_PF_CAPS_D_NUM_UARS_M,

					     V2_QUERY_PF_CAPS_D_NUM_UARS_S);

	caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps,

					    V2_QUERY_PF_CAPS_D_RSV_QPS_M,

					    V2_QUERY_PF_CAPS_D_RSV_QPS_S);

	caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps,

					     V2_QUERY_PF_CAPS_D_RSV_UARS_M,

					     V2_QUERY_PF_CAPS_D_RSV_UARS_S);

	caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws,

					     V2_QUERY_PF_CAPS_E_RSV_MRWS_M,

					     V2_QUERY_PF_CAPS_E_RSV_MRWS_S);

	caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws,

					 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M,

					 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S);

	caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs,

					    V2_QUERY_PF_CAPS_E_RSV_CQS_M,

					    V2_QUERY_PF_CAPS_E_RSV_CQS_S);

	caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs,

					     V2_QUERY_PF_CAPS_E_RSV_SRQS_M,

					     V2_QUERY_PF_CAPS_E_RSV_SRQS_S);

	caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey,

					     V2_QUERY_PF_CAPS_E_RSV_LKEYS_M,

					     V2_QUERY_PF_CAPS_E_RSV_LKEYS_S);

	caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS);

	caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE);

	caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);

	caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH);

	caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS);

	caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH);

	caps->default_aeq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);

	caps->default_ceq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);

	caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS);

	caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS);

	caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS);

	caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS);



	caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS);

	caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT);

	caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS);

	caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS);

	caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS);

	caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);

	caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);

	caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
@@ -2335,15 +2287,9 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 
	caps->cqe_hop_num = pbl_hop_num;

	caps->srqwqe_hop_num = pbl_hop_num;

	caps->idx_hop_num = pbl_hop_num;

	caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,

					  V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M,

					  V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S);

	caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,

					  V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M,

					  V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S);

	caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,

					  V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M,

					  V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S);

	caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM);

	caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM);

	caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM);



	return 0;

}
@@ -5551,7 +5497,7 @@ static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 
				   (eq->cons_index & (eq->entries - 1)) *

				   eq->eqe_size);



	return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^

	return (hr_reg_read(aeqe, AEQE_OWNER) ^

		!!(eq->cons_index & eq->entries)) ? aeqe : NULL;

}
@@ -5571,15 +5517,9 @@ static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 
		 */

		dma_rmb();



		event_type = roce_get_field(aeqe->asyn,

					    HNS_ROCE_V2_AEQE_EVENT_TYPE_M,

					    HNS_ROCE_V2_AEQE_EVENT_TYPE_S);

		sub_type = roce_get_field(aeqe->asyn,

					  HNS_ROCE_V2_AEQE_SUB_TYPE_M,

					  HNS_ROCE_V2_AEQE_SUB_TYPE_S);

		queue_num = roce_get_field(aeqe->event.queue_event.num,

					   HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,

					   HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);

		event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE);

		sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE);

		queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM);



		switch (event_type) {

		case HNS_ROCE_EVENT_TYPE_PATH_MIG:
@@ -5639,8 +5579,8 @@ static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 
				   (eq->cons_index & (eq->entries - 1)) *

				   eq->eqe_size);



	return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^

		(!!(eq->cons_index & eq->entries)) ? ceqe : NULL;

	return (hr_reg_read(ceqe, CEQE_OWNER) ^

		!!(eq->cons_index & eq->entries)) ? ceqe : NULL;

}



static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
@@ -5656,8 +5596,7 @@ static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 
		 */

		dma_rmb();



		cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M,

				     HNS_ROCE_V2_CEQE_COMP_CQN_S);

		cqn = hr_reg_read(ceqe, CEQE_CQN);



		hns_roce_cq_completion(hr_dev, cqn);

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+40 −118
Original line number Diff line number Diff line
@@ -291,33 +291,6 @@ struct hns_roce_v2_cq_context { 
#define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0

#define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL	0x0



#define	V2_CQC_BYTE_4_ARM_ST_S 6

#define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)



#define	V2_CQC_BYTE_4_CEQN_S 15

#define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)



#define	V2_CQC_BYTE_8_CQN_S 0

#define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)



#define	V2_CQC_BYTE_16_CQE_HOP_NUM_S 30

#define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)



#define	V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0

#define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)



#define	V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0

#define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)



#define	V2_CQC_BYTE_52_CQE_CNT_S 0

#define	V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)



#define	V2_CQC_BYTE_56_CQ_MAX_CNT_S 0

#define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)



#define	V2_CQC_BYTE_56_CQ_PERIOD_S 16

#define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)



#define CQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cq_context, h, l)



#define CQC_CQ_ST CQC_FIELD_LOC(1, 0)
@@ -981,7 +954,10 @@ struct hns_roce_func_clear { 
	__le32 rsv[4];

};



#define FUNC_CLEAR_RST_FUN_DONE_S 0

#define FUNC_CLEAR_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_func_clear, h, l)



#define FUNC_CLEAR_RST_FUN_DONE FUNC_CLEAR_FIELD_LOC(32, 32)



/* Each physical function manages up to 248 virtual functions, it takes up to

 * 100ms for each function to execute clear. If an abnormal reset occurs, it is

 * executed twice at most, so it takes up to 249 * 2 * 100ms.
@@ -1222,29 +1198,17 @@ struct hns_roce_query_pf_caps_c { 
	__le16 rq_depth;

};



#define V2_QUERY_PF_CAPS_C_NUM_PDS_S 0

#define V2_QUERY_PF_CAPS_C_NUM_PDS_M GENMASK(19, 0)



#define V2_QUERY_PF_CAPS_C_CAP_FLAGS_S 20

#define V2_QUERY_PF_CAPS_C_CAP_FLAGS_M GENMASK(31, 20)



#define V2_QUERY_PF_CAPS_C_NUM_CQS_S 0

#define V2_QUERY_PF_CAPS_C_NUM_CQS_M GENMASK(19, 0)



#define V2_QUERY_PF_CAPS_C_MAX_GID_S 20

#define V2_QUERY_PF_CAPS_C_MAX_GID_M GENMASK(28, 20)



#define V2_QUERY_PF_CAPS_C_CQ_DEPTH_S 0

#define V2_QUERY_PF_CAPS_C_CQ_DEPTH_M GENMASK(22, 0)

#define PF_CAPS_C_FIELD_LOC(h, l) \

	FIELD_LOC(struct hns_roce_query_pf_caps_c, h, l)



#define V2_QUERY_PF_CAPS_C_NUM_MRWS_S 0

#define V2_QUERY_PF_CAPS_C_NUM_MRWS_M GENMASK(19, 0)



#define V2_QUERY_PF_CAPS_C_NUM_QPS_S 0

#define V2_QUERY_PF_CAPS_C_NUM_QPS_M GENMASK(19, 0)



#define V2_QUERY_PF_CAPS_C_MAX_ORD_S 20

#define V2_QUERY_PF_CAPS_C_MAX_ORD_M GENMASK(27, 20)

#define PF_CAPS_C_NUM_PDS PF_CAPS_C_FIELD_LOC(19, 0)

#define PF_CAPS_C_CAP_FLAGS PF_CAPS_C_FIELD_LOC(31, 20)

#define PF_CAPS_C_NUM_CQS PF_CAPS_C_FIELD_LOC(51, 32)

#define PF_CAPS_C_MAX_GID PF_CAPS_C_FIELD_LOC(60, 52)

#define PF_CAPS_C_CQ_DEPTH PF_CAPS_C_FIELD_LOC(86, 64)

#define PF_CAPS_C_NUM_MRWS PF_CAPS_C_FIELD_LOC(115, 96)

#define PF_CAPS_C_NUM_QPS PF_CAPS_C_FIELD_LOC(147, 128)

#define PF_CAPS_C_MAX_ORD PF_CAPS_C_FIELD_LOC(155, 148)



struct hns_roce_query_pf_caps_d {

	__le32 wq_hop_num_max_srqs;
@@ -1255,20 +1219,26 @@ struct hns_roce_query_pf_caps_d { 
	__le32 num_uars_rsv_pds;

	__le32 rsv_uars_rsv_qps;

};

#define V2_QUERY_PF_CAPS_D_NUM_SRQS_S 0

#define V2_QUERY_PF_CAPS_D_NUM_SRQS_M GENMASK(19, 0)



#define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S 20

#define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M GENMASK(21, 20)



#define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S 22

#define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M GENMASK(23, 22)



#define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S 24

#define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M GENMASK(25, 24)



#define V2_QUERY_PF_CAPS_D_CONG_TYPE_S 26

#define V2_QUERY_PF_CAPS_D_CONG_TYPE_M GENMASK(29, 26)

#define PF_CAPS_D_FIELD_LOC(h, l) \

	FIELD_LOC(struct hns_roce_query_pf_caps_d, h, l)



#define PF_CAPS_D_NUM_SRQS PF_CAPS_D_FIELD_LOC(19, 0)

#define PF_CAPS_D_RQWQE_HOP_NUM PF_CAPS_D_FIELD_LOC(21, 20)

#define PF_CAPS_D_EX_SGE_HOP_NUM PF_CAPS_D_FIELD_LOC(23, 22)

#define PF_CAPS_D_SQWQE_HOP_NUM PF_CAPS_D_FIELD_LOC(25, 24)

#define PF_CAPS_D_CONG_TYPE PF_CAPS_D_FIELD_LOC(29, 26)

#define PF_CAPS_D_CEQ_DEPTH PF_CAPS_D_FIELD_LOC(85, 64)

#define PF_CAPS_D_NUM_CEQS PF_CAPS_D_FIELD_LOC(95, 86)

#define PF_CAPS_D_AEQ_DEPTH PF_CAPS_D_FIELD_LOC(117, 96)

#define PF_CAPS_D_AEQ_ARM_ST PF_CAPS_D_FIELD_LOC(119, 118)

#define PF_CAPS_D_CEQ_ARM_ST PF_CAPS_D_FIELD_LOC(121, 120)

#define PF_CAPS_D_RSV_PDS PF_CAPS_D_FIELD_LOC(147, 128)

#define PF_CAPS_D_NUM_UARS PF_CAPS_D_FIELD_LOC(155, 148)

#define PF_CAPS_D_RSV_QPS PF_CAPS_D_FIELD_LOC(179, 160)

#define PF_CAPS_D_RSV_UARS PF_CAPS_D_FIELD_LOC(187, 180)



#define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12



struct hns_roce_congestion_algorithm {

	u8 alg_sel;
@@ -1277,33 +1247,6 @@ struct hns_roce_congestion_algorithm { 
	u8 wnd_mode_sel;

};



#define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S 0

#define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M GENMASK(21, 0)



#define V2_QUERY_PF_CAPS_D_NUM_CEQS_S 22

#define V2_QUERY_PF_CAPS_D_NUM_CEQS_M GENMASK(31, 22)



#define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S 0

#define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M GENMASK(21, 0)



#define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S 22

#define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M GENMASK(23, 22)



#define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S 24

#define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M GENMASK(25, 24)



#define V2_QUERY_PF_CAPS_D_RSV_PDS_S 0

#define V2_QUERY_PF_CAPS_D_RSV_PDS_M GENMASK(19, 0)



#define V2_QUERY_PF_CAPS_D_NUM_UARS_S 20

#define V2_QUERY_PF_CAPS_D_NUM_UARS_M GENMASK(27, 20)



#define V2_QUERY_PF_CAPS_D_RSV_QPS_S 0

#define V2_QUERY_PF_CAPS_D_RSV_QPS_M GENMASK(19, 0)



#define V2_QUERY_PF_CAPS_D_RSV_UARS_S 20

#define V2_QUERY_PF_CAPS_D_RSV_UARS_M GENMASK(27, 20)



struct hns_roce_query_pf_caps_e {

	__le32 chunk_size_shift_rsv_mrws;

	__le32 rsv_cqs;
@@ -1315,20 +1258,14 @@ struct hns_roce_query_pf_caps_e { 
	__le16 aeq_period;

};



#define V2_QUERY_PF_CAPS_E_RSV_MRWS_S 0

#define V2_QUERY_PF_CAPS_E_RSV_MRWS_M GENMASK(19, 0)



#define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S 20

#define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M GENMASK(31, 20)



#define V2_QUERY_PF_CAPS_E_RSV_CQS_S 0

#define V2_QUERY_PF_CAPS_E_RSV_CQS_M GENMASK(19, 0)

#define PF_CAPS_E_FIELD_LOC(h, l) \

	FIELD_LOC(struct hns_roce_query_pf_caps_e, h, l)



#define V2_QUERY_PF_CAPS_E_RSV_SRQS_S 0

#define V2_QUERY_PF_CAPS_E_RSV_SRQS_M GENMASK(19, 0)



#define V2_QUERY_PF_CAPS_E_RSV_LKEYS_S 0

#define V2_QUERY_PF_CAPS_E_RSV_LKEYS_M GENMASK(19, 0)

#define PF_CAPS_E_RSV_MRWS PF_CAPS_E_FIELD_LOC(19, 0)

#define PF_CAPS_E_CHUNK_SIZE_SHIFT PF_CAPS_E_FIELD_LOC(31, 20)

#define PF_CAPS_E_RSV_CQS PF_CAPS_E_FIELD_LOC(51, 32)

#define PF_CAPS_E_RSV_SRQS PF_CAPS_E_FIELD_LOC(83, 64)

#define PF_CAPS_E_RSV_LKEYS PF_CAPS_E_FIELD_LOC(115, 96)



struct hns_roce_cmq_req {

	__le32 data[6];
@@ -1413,9 +1350,6 @@ struct hns_roce_dip { 
#define HNS_ROCE_EQ_INIT_CONS_IDX		0

#define HNS_ROCE_EQ_INIT_NXT_EQE_BA		0



#define HNS_ROCE_V2_CEQ_CEQE_OWNER_S		31

#define HNS_ROCE_V2_AEQ_AEQE_OWNER_S		31



#define HNS_ROCE_V2_COMP_EQE_NUM		0x1000

#define HNS_ROCE_V2_ASYNC_EQE_NUM		0x1000
@@ -1472,18 +1406,6 @@ struct hns_roce_eq_context { 
#define EQC_NEX_EQE_BA_H EQC_FIELD_LOC(339, 320)

#define EQC_EQE_SIZE EQC_FIELD_LOC(341, 340)



#define HNS_ROCE_V2_CEQE_COMP_CQN_S 0

#define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)



#define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0

#define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)



#define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8

#define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8)



#define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0

#define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)



#define MAX_SERVICE_LEVEL 0x7



struct hns_roce_wqe_atomic_seg {

drivers/infiniband/hw/hns/hns_roce_restrack.c

+14 −35
Original line number Diff line number Diff line
@@ -13,61 +13,40 @@ static int hns_roce_fill_cq(struct sk_buff *msg, 
			    struct hns_roce_v2_cq_context *context)

{

	if (rdma_nl_put_driver_u32(msg, "state",

				   roce_get_field(context->byte_4_pg_ceqn,

						  V2_CQC_BYTE_4_ARM_ST_M,

						  V2_CQC_BYTE_4_ARM_ST_S)))

				   hr_reg_read(context, CQC_ARM_ST)))



		goto err;



	if (rdma_nl_put_driver_u32(msg, "ceqn",

				   roce_get_field(context->byte_4_pg_ceqn,

						  V2_CQC_BYTE_4_CEQN_M,

						  V2_CQC_BYTE_4_CEQN_S)))

				   hr_reg_read(context, CQC_CEQN)))

		goto err;



	if (rdma_nl_put_driver_u32(msg, "cqn",

				   roce_get_field(context->byte_8_cqn,

						  V2_CQC_BYTE_8_CQN_M,

						  V2_CQC_BYTE_8_CQN_S)))

				   hr_reg_read(context, CQC_CQN)))

		goto err;



	if (rdma_nl_put_driver_u32(msg, "hopnum",

				   roce_get_field(context->byte_16_hop_addr,

						  V2_CQC_BYTE_16_CQE_HOP_NUM_M,

						  V2_CQC_BYTE_16_CQE_HOP_NUM_S)))

				   hr_reg_read(context, CQC_CQE_HOP_NUM)))

		goto err;



	if (rdma_nl_put_driver_u32(

		    msg, "pi",

		    roce_get_field(context->byte_28_cq_pi,

				   V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M,

				   V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S)))

	if (rdma_nl_put_driver_u32(msg, "pi",

				   hr_reg_read(context, CQC_CQ_PRODUCER_IDX)))

		goto err;



	if (rdma_nl_put_driver_u32(

		    msg, "ci",

		    roce_get_field(context->byte_32_cq_ci,

				   V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M,

				   V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S)))

	if (rdma_nl_put_driver_u32(msg, "ci",

				   hr_reg_read(context, CQC_CQ_CONSUMER_IDX)))

		goto err;



	if (rdma_nl_put_driver_u32(

		    msg, "coalesce",

		    roce_get_field(context->byte_56_cqe_period_maxcnt,

				   V2_CQC_BYTE_56_CQ_MAX_CNT_M,

				   V2_CQC_BYTE_56_CQ_MAX_CNT_S)))

	if (rdma_nl_put_driver_u32(msg, "coalesce",

				   hr_reg_read(context, CQC_CQ_MAX_CNT)))

		goto err;



	if (rdma_nl_put_driver_u32(

		    msg, "period",

		    roce_get_field(context->byte_56_cqe_period_maxcnt,

				   V2_CQC_BYTE_56_CQ_PERIOD_M,

				   V2_CQC_BYTE_56_CQ_PERIOD_S)))

	if (rdma_nl_put_driver_u32(msg, "period",

				   hr_reg_read(context, CQC_CQ_PERIOD)))

		goto err;



	if (rdma_nl_put_driver_u32(msg, "cnt",

				   roce_get_field(context->byte_52_cqe_cnt,

						  V2_CQC_BYTE_52_CQE_CNT_M,

						  V2_CQC_BYTE_52_CQE_CNT_S)))

				   hr_reg_read(context, CQC_CQE_CNT)))

		goto err;



	return 0;